Fast and accurate SEU-tolerance characterization method for Zynq SoCs

Abstract

In this paper a new SEU (Single Event Upset) emulation method for testing fault tolerant systems in FPGAs is presented. It is implemented on a "Xilinx Zynq®-7000 All Programmable System on Chip (SoC)" device, which combines a hard microprocessor with programmable logic. An important new feature is that an internal hardware configuration interface controlled by this microprocessor is provided. This interface is used for injecting faults into the configuration bitstream in order to emulate radiation effects. Since both the processing system and the programmable logic are in the same chip, this method has the high speed characteristics of internal fault injection methods. As a hard internal configuration interface is provided, a configuration bit belonging to the internal interface port cannot be flipped and injection side effects are avoided. This method is especially suitable for testing complex real fault-tolerant FPGA designs because no substantial modifications need to be added to the original design. A universal verification system is proposed to avoid designing complex external application-dependent testbenches.

A Generic Methodology to Compute Design Sensitivity to SEU in SRAM-Based FPGA

“…In addition, for each design, partial vulnerability factor associated to each memory type is calculated and represented [29] which estimates that no more than 0.11 fraction of configuration bits are critical, even when the whole FPGA is used. In addition and as expected this result is similar to results reported in [24] for ADDER implemented in Zynq-7000. Configuration bits corresponding to routing elements are more sensible than the ones used in LUTs, as roughly 80% of failures are due to SEU in routing elements [19].…”

“…A lot of efforts has been already spent looking into soft-error effects in SRAM-Based FPGAs: simulation-based, radiationbased, modeling and analysis-based approaches [13]- [24]. The first two approaches mainly exploit Fault-Injection strategies where the process of fault injection is achieved either using simulation tools or radiation equipment.…”

“…In simulation-based methods [17]- [24], SEU effects are estimated with flipping bits of CM while running a design on FPGA.…”

Field Programmable Gate Array Applications—A Scientometric Review

“…[1477][1478][1479] and image processing [1480][1481][1482][1483][1484][1485][1486][1487]. Finally, the blue cluster shows that the fault tolerance and high reliability systems are based in fault injection impelmentations [1488,1489] and single event upset tolerance mechanisms [1490][1491][1492]. In addition, other relevant relations are shown in colored lines, like digital control with PWM [1493,1494], simulation with modeling [1057,1118,1495] and performance with algorithms [1496][1497][1498].…”

Fault‐tolerant method for anti‐SEU of embedded system based on dual‐core processor

“…However, Zynq series chips have low radiation resistance and are susceptible to occur single event upsets (SEUs) [6, 7] in the space environment due to various high‐energy particles and rays. SEUs can invalidate the function of the circuit and even lead to the system catastrophic consequences.…”