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This paper introduces an experimental test-flow for evaluating the susceptibility of SRAM based FPGA designs to SEU (Single Event Upsets). Using this method it is possible to cover both SEUs and MBU (Multiple Bit Upsets) in the configuration memory of Xilinx FPGAs for applications based on tiny soft microprocessors.The introduced test-flow imposes a minimal effort to the system developer and achieves a good estimation on the percentage of critical bits in the configuration memory of a design. This flow is executed for a design using multiple tiny soft microprocessors and the reliability values extracted by the test-flow are compared to non-experimental estimation techniques.

In this paper a new SEU (Single Event Upset) emulation method for testing fault tolerant systems in FPGAs is presented. It is implemented on a "Xilinx Zynq®-7000 All Programmable System on Chip (SoC)" device, which combines a hard microprocessor with programmable logic. An important new feature is that an internal hardware configuration interface controlled by this microprocessor is provided. This interface is used for injecting faults into the configuration bitstream in order to emulate radiation effects. Since both the processing system and the programmable logic are in the same chip, this method has the high speed characteristics of internal fault injection methods. As a hard internal configuration interface is provided, a configuration bit belonging to the internal interface port cannot be flipped and injection side effects are avoided. This method is especially suitable for testing complex real fault-tolerant FPGA designs because no substantial modifications need to be added to the original design. A universal verification system is proposed to avoid designing complex external application-dependent testbenches.

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