Robustness Analysis of Different AES Implementations on SRAM Based FPGAs

Kretzschmar, Uli; Astarloa, Armando; ́zaro, Jesus L; Bidarte, Unai; Jiménez, Jaime

doi:10.1109/reconfig.2011.80

Cited by 8 publications

(5 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Comparing SBE test flow emulation time of this hypothetical design against a complete external injection like in [2] results in a SBE accuracy dependent speed up as shown in Figure 3c . For an SBE accuracy of 90% the speed up is 50 times, for 99.9% still 6 times as fast.…”

Section: B Example Calculationsmentioning

confidence: 99%

“…by multiplying the amount of FPGA resources used by the number of configuration bits for each of these resources.The number of configuration bits B dev can be found in [11]. Not all single bit errors in the configuration bits corresponding to the SEU controller are critical, in fact [2] found that 9% of the bits are critical for a design using PicoBlaze microcontrollers (which is the basis for the SEU controller) to compute AES. Considering this P hit SEU,con represents the probability that a critical bit of the SEU controller was hit, with p ctr being the SEU controller critical bit ratio P hit SEU,con =P hit SEU · p ctr .…”

Section: A Sbe Accuracy Without Time Redundancymentioning

confidence: 99%

“…The need of efficient methods of SEU resilience testing is further fed by the fact, that even different implementation of the same functionality results in different SEU resiliences, as demonstrated for AES in [2]. Various methods have been proposed in the literature, where most are slow due to the long device configuration time or they are prone to what will be called injection side effects in this work.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Fast and accurate Single Bit Error injection into SRAM Based FPGAs

Kretzschmar

Astarloa

Jiménez

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of errors. One error type, Single Event Upsets (SEU), are rare events, so technologies of either external-or internal error injection are used to emulate this kind of error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects.This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.

show abstract

Section: B Example Calculationsmentioning

confidence: 99%

Section: A Sbe Accuracy Without Time Redundancymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Fast and accurate Single Bit Error injection into SRAM Based FPGAs

Kretzschmar

Astarloa

Jiménez

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

show abstract

“…Sub Byte development gives the abnormality figure. The S Box utilized is gotten with the multiplicative opposite finished Galois Field (28) [7], inconceivable without linearity property. Different S-Box execution [7] utilize combinational circuit includes a snake, squarer and unsurprising multipliers.…”

Section: Asubbyte and Inverse Subbyte Changementioning

confidence: 99%

A Classical Methodology of AES Algorithm using Cipher Key

Palamarthi,

Krishna

2019

IJEAT

View full text Add to dashboard Cite

Expanding might want information insurance in PC systems diode to the occasion of numerous cryptanalytic calculations hence causing information immovably over a transmission connect is basically vital in a few applications. Equipment usage of cryptanalytic calculations square measure physically secure than bundle executions since outside aggressors can't change them. So as to accomplish better in the present intensely stacked correspondence systems, equipment execution could be an insightful choice as far as higher speed and dependableness. In This paper shows the gear utilization of Advanced cryptography dynamic (AES) rule abuse Xilinx-virtex five Field Programmable Gate Array .In solicitation to achieve higher tempo and lesser freedom Sub PC memory unit movement, Inverse Sub PC mu action, join Column action and Inverse solidify Column assignments square measure arranged as LUTs and Read Only Memorie .

show abstract

“…Sub Byte development gives the abnormality figure. The S Box utilized is gotten with the multiplicatives opposite finished Galois Field (28) [7], inconceivable without linearity property. Different S-Box execution [7] utilize combinational circuit includes a snake, squarer and unsurprising multipliers.…”

Section: Advanced Encryption Standardmentioning

confidence: 99%

A Classical Scheme of AES algorithm using Cipher key

2019

IJRTE

View full text Add to dashboard Cite

show abstract

Robustness Analysis of Different AES Implementations on SRAM Based FPGAs

Cited by 8 publications

References 8 publications

Fast and accurate Single Bit Error injection into SRAM Based FPGAs

Fast and accurate Single Bit Error injection into SRAM Based FPGAs

A Classical Methodology of AES Algorithm using Cipher Key

A Classical Scheme of AES algorithm using Cipher key

Contact Info

Product

Resources

About