Fast and accurate Single Bit Error injection into SRAM Based FPGAs

Abstract

The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of errors. One error type, Single Event Upsets (SEU), are rare events, so technologies of either external-or internal error injection are used to emulate this kind of error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects.This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

“…Moreover, the implementation of a different fault injection methodology which considers the complete configuration memory array [32] could be a helpful idea in order to obtain the reliability level of the entire system.…”

A Survey of QEMU-Based Fault Injection Tools & Techniques for Emulating Physical Faults

“…Single event transients (SETs) are transient voltage pulses generated at the output gates by a particle striking a chip surface [37]. The resulting error from a SET propagating to a memory element and stored in it is called a soft error.…”