Fast and Accurate Waveform Analysis with Current Source Models

Rapid design space exploration using legacy design data and technology scaling trend

“…These tools operate on detailed transistor level netlist. Experiments on ISCAS circuits implemented in a 90 nm industrial process using a lumped capacitance model and the most commonly used Thevenin based flow for timing analysis yielded errors between 10% and 15% (reported mþs error quantile of 7.5%) [40]. With this context, operating at the highest level of abstraction and with power and performance prediction errors in the range of 9-22% compared to SPICE results makes the usage of EIDA for high level design tradeoffs practical, especially for the early design phase when complete bottom up data is not available yet.…”

Semi-analytical current source modeling of near-threshold operating logic cells considering process variations

“…Thus, it is much faster compared to the circuit simulator such as the HSPICE, which solves for these information iteratively all the time. Thanks to these capabilities, CSM methods are used in the timing analysis and effectively reduce the errors in delay calculation [8].…”

Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling

“…The Miller effect between the input and output nodes was ignored in this model. In [8], a Blade-based model is used and the input and output voltage waveforms are approximated with Weibull functions. Keller et al [9] presented a CS model for the purpose of crosstalk noise analysis.…”