Fast and Area-Efficient SRAM Word-Line Optimization

Abstract

A word line driver controls the access of cells in a row in Static Random Access Memories (SRAMs) and has a significant impact on SRAM speed and power consumption. When gate delay is the dominant factor, simple models are a good guideline for fast word lines. However, routing wire delay is significant when the row size is large, which causes these designs to be suboptimal. This paper presents an analytical optimization technique using a delay model that includes gate delay, wire resistance, and wire capacitance to optimize high-performance word line driver topologies for SRAMs. The proposed methodology has a maximum 45% delay improvement and 42% buffer cost reduction.

Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization

“…The DWL with buffer insertion is a hard problem and applying buffer insertion to a naive single word line topology is an important subproblem of it. For a given row size, the best 978-1-7281-3915-9/19/$31.00 c 2019 IEEE topology of a DWL is not trivial as the segments are not the same size to achieve the smallest delay [9]. Hence, different topologies must be iterated over for a DWL buffer insertion optimization while a standard buffer insertion requires a fixed topology.…”