Fast and compact controllers with digital neural networks

Lazzizzera, I.; Tecchiolii, G.; Lee, P.; Zorat, Alessandro; Sartori, A.

doi:10.1109/imtc.1997.603947

Cited by 1 publication

(4 citation statements)

References 11 publications

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“…by using its linear approximation in the interval [1,2). As observed in [6], the difference between lg f and f −1 in such interval is bounded from above by 0.0862 so the maximum error incurred by the proposed approximation is less than 9% of the arithmetically correct value.…”

Section: Pseudo-logarithmic Number Representationmentioning

confidence: 80%

“…The approach proposed here is an evolution of the one presented in [6] and is based on the observation that the complexity for a hardware realization of a multiplier is higher than that of an adder. At the same time, when using a logarithmic number system, the log(x × y) becomes log x + log y, thus transforming a multiplication into a sum.…”

Section: Pseudo-logarithmic Number Representationmentioning

confidence: 99%

“…In [6] the definition of the pseudo-logarithmic function plg x has been introduced to approximate the base-two logarithm of a real positive number x. Briefly, the original number x is decomposed into two parts as x = 2 n × f , with n such that 2 n ≤ x < 2 n+1 .…”

Section: Pseudo-logarithmic Number Representationmentioning

confidence: 99%

“…To test the SVM classifier, several data have been collected according to equations (6) and to the following model:…”

Section: A Channel Equalizationmentioning

confidence: 99%

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FPGA Implementation of Support Vector Machines with Pseudo-Logarithmic Number Representation

Boni

Zorat

2006

The 2006 IEEE International Joint Conference on Neural Network Proceedings

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Computations in Support Vector Machines (SVM)involve a large number of vector multiplications. When implementing such architectures on a stand alone, embedded system, the complexity of the hardware implementation of the multipliers can be a limiting factor. This paper proposes a representation of numerical data to be processed by an approximation of the logarithm of the number, thus allowing the substitution of expensive multipliers with simpler adders. Additional circuitry is proposed to translate between standard and the proposed pseudo-logarithmic number representation.The operations for the representation translation, addition and multiplication with pseudo-logarithmic numbers have been implemented in software and several experiments have been carried out to assess their performance when used in a SVM-based computational architecture that was used for data classification. The results obtained show that the proposed representation yields an accuracy that is comparable with that obtained by using standard floating point or fixed point number representation.

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Section: Pseudo-logarithmic Number Representationmentioning

confidence: 80%

Section: Pseudo-logarithmic Number Representationmentioning

confidence: 99%

Section: Pseudo-logarithmic Number Representationmentioning

confidence: 99%

“…To test the SVM classifier, several data have been collected according to equations (6) and to the following model:…”

Section: A Channel Equalizationmentioning

confidence: 99%

See 2 more Smart Citations