FPGA Implementation of Support Vector Machines with Pseudo-Logarithmic Number Representation

Abstract

Computations in Support Vector Machines (SVM)involve a large number of vector multiplications. When implementing such architectures on a stand alone, embedded system, the complexity of the hardware implementation of the multipliers can be a limiting factor. This paper proposes a representation of numerical data to be processed by an approximation of the logarithm of the number, thus allowing the substitution of expensive multipliers with simpler adders. Additional circuitry is proposed to translate between standard and the proposed pseudo-logarithmic number representation.The operations for the representation translation, addition and multiplication with pseudo-logarithmic numbers have been implemented in software and several experiments have been carried out to assess their performance when used in a SVM-based computational architecture that was used for data classification. The results obtained show that the proposed representation yields an accuracy that is comparable with that obtained by using standard floating point or fixed point number representation.

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

“…However, low resource consuming implementations of CORDIC algorithms have increased latency [10]. Other works [26], [27] propose that computations are done in the logarithmic number system, where multiplications are replaced with additions, in order to reduce the required processing resources. However, they only consider a single processing module, hence, when adopting a more parallel architecture, to facilitate real-time operation, the additional cost from converting between the decimal number system to the logarithmic one and back again for all inputs increases.…”

Boosting the Hardware-Efficiency of Cascade Support Vector Machines for Embedded Classification Applications

“…However, they only consider a single processing module, hence, when adopting a more parallel architecture, to facilitate real-time operation, the additional cost from converting between the decimal number system to the logarithmic one and back again for all inputs increases. Alternatively, a pseudo-logarithmic number system was proposed in [35], however, the overhead for converting between number systems, in order to perform additions, remains. The works in [36], [37], [38] have looked at how the bitwidth precision impacts the classification error, in an effort to find the best trade-off between hardware resources, performance and classification speed.…”

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