Fast and Cycle-Accurate Simulation of RTL NoC Designs Using Test-Driven Cellular Automata

Abstract

Speeding up the register-transfer level (RTL) simulation of network-on-chip (NoC) is essential for design optimization under various use scenarios and parameters. One of the promising approaches for RTL NoC speedup is high-level modeling. Conventional high-level modeling approaches lead to an accuracy problem or modeling efforts that are caused by the absence of modeling framework or requiring in-depth knowledge of specific behaviors of target NoCs. To support cycle-accurate and formal high-level modeling framework, we propose a cellular automata (CA) modeling framework for RTL NoC. The CA abstracts detailed RTL NoC dynamics into the proposed high-level state transitions, which support flit transmission among CA components through dynamically changing flit paths based on the target RTL routing and arbitration algorithms. To prevent the meaningless execution of stable CA, the CA are designed to be triggered by state-change events. The proposed simulation engine asynchronously invokes CA to update their states and perform actions of flit transmissions or flit-path changes based on the state-decision result. To reduce the modeling difficulty, we provide a test environment that generates the state-transition rules for CA after monitoring the relationships between high-level states and leading actions under randomly injected packets during target RTL NoC simulations. Experiments demonstrate cycle-level functional homogeneity between RTL and the abstracted CA NoC models and significant simulation speedup. INDEX TERMS Network on chip, cellular automata, RTL design, test-driven rule generation, event-based simulation. FIGURE 2. Examples of CA network and BC mappings.