Fast and efficient power estimation model for FPGA based designs

Tripathi, Abhishek; Rajawat, Arvind

doi:10.1016/j.micpro.2018.03.005

Cited by 3 publications

(2 citation statements)

References 5 publications

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“…It predicts cycle-wise power and is comparable with a commercial gate-level power estimation tools. A model is presented in [ 7 ] for dynamic power estimation for specific applications implemented on FPGAs. A profiling-based neural network model is used for dynamic power estimation.…”

Section: Literature Reviewmentioning

confidence: 99%

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

Siddiq

Durrani

2022

PLoS ONE

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Low-power consumption has been always a crucial design constraint for an efficient intellectual property based three-dimensional multi-core system that cannot be ignored easily. As the complexity increases due to the number of cores/stacks/ layers in 3D digital systems, the challenges to handle power can be more difficult at a high abstraction level. Therefore, the low-power approach gives designers an opportunity to estimate and optimize the power consumption in the early stages of design phases. The accurate power estimation through the macro-modeling approach at high-level reduces the risk of redesign cycle and turn-around time. In this research, we have presented an improved statistical macro-modeling approach that estimates power through statistical characteristics of randomly generated input patterns by using Biogeography Based Optimization. These input patterns propagate signals into an IP-based 3D digital test system. In experiments, the test system is based on four 8 to 32- bits heterogeneous cores. The response of the power is monitored by applying the well-known Monte Carlo Simulation technique. The entire power estimation method is performed in two major steps. First, the average power is estimated for an IP-based individual core. Second, the average power for bus-based Through-Silicon-Via is estimated. Finally, the cores and B-TSVs are integrated together to construct a 3D system. Then the average power for complete test systems is estimated. The experimental results of the statistical power macro-model are compared with the commercial Electronic Design Automation power simulator at the operating frequency of 100 MHz. The average percentage error of the test system is calculated as 8.65%. For the validation of these results, the statistical error analysis is additionally performed and reveals that our proposed macro-model is accurate in terms of percentage of error with a feasible amount of time.

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Section: Literature Reviewmentioning

confidence: 99%

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

Siddiq

Durrani

2022

PLoS ONE

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“…In the same context, authors in [99] provide power estimate using artificial neural networks. As a result, an average relative error of 3.97% is obtained.…”

Section: Neural Network Based Techniquesmentioning

confidence: 99%

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

Nasser

Lorandel

Prévotet

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Power consumption constitutes a major challenge for electronics circuits. One possible way to deal with this issue is to consider it very soon in the design process in order to explore various design choices. A typical design flow often starts with a high-level description of a full system, which imposes to provide accurate models. Power modelling techniques can be employed, providing a way to find a relationship between power and other metrics. Furthermore, it is also important to consider efficient power characterization techniques. The role of this paper is, first, to provide an overview of RTL to transistor level power modelling and estimation techniques for FPGAs and ASICs devices. Second, it aims at proposing a classification of all approaches according to defined metrics, which should help designers in finding a particular method for their specific situation, even if no common reference is defined among the considered works. Index Terms-Power consumption, power modelling, power estimation, high-level power estimation, FPGA, ASIC, tools.. Antifuse Technology (e.g., Actel TM , Quicklogic TM): an antifuse remains in a high-impedance state until it is programmed into a low-impedance or "fused" state (Figure 9.18). This technology can be used only once on one-time programmable (OTP) devices; it is less expensive than the RAM technology.

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Power Estimation and Validation of Embedded Multiplier Based on ANN and Regression Technique

Singh

Verma

Khare

2021

J CIRCUIT SYST COMP

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Nowadays, high-end Field-Programmable Gate Arrays (FPGAs) are capable of implementing relatively high-performance systems in the field of Digital Signal Processing (DSP). Due to the abundant application of multipliers, their implementation efficiency and performance have become a critical issue in designing the DSP systems. On the other hand, FPGAs consume a large amount of power due to their complex circuitry. So, the power estimation of FPGA implementations at an early design stage has become a critical design metric. Various models are available in the literature based on Look-up Tables (LUTs), but not much literature is available on speed-optimized multiplier design using DSP slices only. In this paper, an embedded multiplier (12.0 IP core) has been analyzed and customized for different Input/Output (I/O) configurations to estimate the power using Vivado Design Suite (2014.4) targeted to the Zynq-family FPGA device (Zynq evolution and development kit). The embedded multiplier IP has been optimized for performance using two different approaches, i.e., Mults (DSP)-based and LUTs-based. Post-synthesis attributes have been used for formulating the power estimation models based on Artificial Neural Network (ANN) and curve fitting and regression technique. The power values estimated from the proposed models have been authenticated with reference to those assessed from the commercial tool. Based on the results obtained, ANN-based model provides average errors of 0.73% and 0.88% for the LUTs and DSP-based designs, respectively. Whereas, the model based on curve fitting and regression technique provides average errors of 3.61% and 1.59% for the LUTs and DSP-based designs, respectively. The timing analysis has been done to get the design performance and time complexity of the proposed models. Area analysis of the design has also been performed in order to report the resource utilization.

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Fast and efficient power estimation model for FPGA based designs

Cited by 3 publications

References 5 publications

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

Power Estimation and Validation of Embedded Multiplier Based on ANN and Regression Technique

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