Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms

Abstract

In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.

Single-Objective Optimization of a CMOS VCO Considering PVT and Monte Carlo Simulations

“…The VCO optimization has been carried out through different approaches, such as metaheuristics [7,22]. In [7], a ring VCO's operation improvement is performed through particle swam optimization (PSO) and non-dominated sorting genetic algorithm (NSGA-II), to minimize both the phase noise and the power consumption.…”

“…Achieving also an improvement in tuning range without being an objective and also performing both Monte Carlo and process corners analyses to the final design. Similarly, in [22] the optimal sizing of a differential ring VCO is carried out through multi-objective particle swam optimization (MOPSO) and infeasibility-driven evolutionary algorithm (IDEA) to improve its performances by minimizing both the phase noise and the power consumption while maintaining a given oscillation frequency. Noise modeling is also carried out, to obtain the simplified noise expressions and solve the equations' system the determinate decision diagram (DDD) symbolic technique is used.…”

“…f osc varies in a range determined by a control voltage V ctrl [14], and depends on the number of CMOS differential stages N, but decreasing N yields a reduction in gain, which may result in the oscillation mitigation. This trade-off can be improved by applying metaheuristics to maximize f osc under a wide range of V ctrl , and low silicon area or number of CMOS differential stages N. Different metaheuristics have been applied to the optimization of CMOS integrated circuits in previous works due to the complexity involved in the design processes [7,[20][21][22]. In this manner, the differential evolution (DE) algorithm is applied herein to vary the sizes of the transistors in the CMOS differential stages to maximize the oscillation frequency of a CMOS VCO f osc .…”

An efficient method to compute simplified noise parameters of analog amplifiers using symbolic and evolutionary approach

“…Several studies have already focused on the exact symbolic noise analysis, without applying any simplification algorithms. 20,21 In Reference 22, MATLAB was used for the symbolic analysis of output referred noise methodology. Also, a matrix-based and a graph-based exact noise analysis technique have been proposed.…”

“…Hence these exact symbolic expressions are not found to be very much useful for the analysis of the practical analog circuits, rather the symbolic expressions are further simplified in accordance with the problem. Several studies have already focused on the exact symbolic noise analysis, without applying any simplification algorithms 20,21 . In Reference 22, MATLAB was used for the symbolic analysis of output referred noise methodology.…”