Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation

Roloff, Sascha; Hannig, Frank; Teich, Jürgen

doi:10.1145/2236576.2236582

Cited by 8 publications

(7 citation statements)

References 19 publications

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“…The simulation of each processor core executing software threads (activities) is done by one simulation thread on the host machine via an execution-driven simulation approach presented in [1]. Here, functional and timing simulation are tightly coupled and can be classified as a so-called timing-directed simulation approach.…”

Section: Execution-driven Processor Simulationmentioning

confidence: 99%

“…Here, functional and timing simulation are tightly coupled and can be classified as a so-called timing-directed simulation approach. During functional simulation, the application code is executed on the host machine and the number n of executed instructions is counted by a performance counter c(d) of the simulation thread d. Each functional simulation phase is followed by a timing simulation phase, where the execution latency ∆t on the target processor is calculated and added to the simulation time t(d) of the simulation thread d. ∆t is determined by a concept called time warping [1], which requires the number of executed instructions n, a couple of properties of the processor …”

Section: Execution-driven Processor Simulationmentioning

confidence: 99%

“…However, micro-architectural details are often not required in many practical design studies at system-level and in advanced parallel software development. With these deficiencies in mind, we propose a high-level simulation concept and tool called InvadeSIM, shown in Figure 1, which uses an approximate time functional simulation approach presented us in [1]. This simulator may tackle the complexity and the heterogeneity of modern multi-core architectures and allows to model different tiled MPSoC architectures, i. e., to support the design exploration of architecture decisions such as number of cores per tile, NoC attributes, and types of cores on each tile.…”

Section: Introductionmentioning

confidence: 99%

“…of the underlying architecture at run-time. The approach in [1] is based on direct execution and analytical modeling techniques. It delivers important timing information about the parallel execution and competition of multiple applications with highly dynamic parallelism profiles.…”

Section: Introductionmentioning

confidence: 99%

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Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures

Roloff

Schafhauser

Hannig

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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We present a parallel execution-driven simulator for the efficient simulation of heterogeneous tile-based multi-core architectures. Here, the architecture is composed of several tiles connected via a network-on-chip and each tile contains local memory as well as several possibly different types of compute resources. Partitioned Global Address Space (PGAS) is a programming model matching very well the needs for programming of such modern multi-core architectures. In order to provide performance estimations for parallel software and enable architecture design space exploration, fast functional and timing simulation techniques are required. Thus, we present a simulator that meets this requirement by combining a fast direct-execution simulation approach with different parallelization strategies. Here, we propose four novel parallel discrete-event simulation techniques, which map threadlevel parallelism within the applications to core-level parallelism on the target architecture and back to thread-level parallelism on the host machine. In order to achieve this, the correct synchronization and activation of the host threads is necessary being the main focus of this paper. Experiments with parallel realworld applications are used to compare the different techniques against each other and demonstrate that 10.4 times faster simulations than a sequential simulation can be achieved on a 12-core Intel Xeon processor.

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Section: Execution-driven Processor Simulationmentioning

confidence: 99%

Section: Execution-driven Processor Simulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures

Roloff

Schafhauser

Hannig

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

Self Cite

View full text Add to dashboard Cite

show abstract

“…The strong point is a significant reduction in time and effort required to obtain results due to reusability of application and platform profiles. Also, the proposed method can be easily scaled for systems with hundred or more elements of the same type, in a similar fashion to the method demonstrated in [11].…”

Section: Introductionmentioning

confidence: 99%

Elementary operations: a novel concept for source-level timing estimation

2019

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Early application timing estimation is essential in decision making during design space exploration of heterogeneous embedded systems in terms of hardware platform dimensioning and component selection. The decisions which have the impact on project duration and cost must be made before a platform prototype is available and software code is ready to be linked and thus timing estimation must be done using high-level models and simulators. Because of the ever increasing need to shorten the time to market, reducing the amount of time required to obtain the results is as important as achieving high estimation accuracy. In this paper, we propose a novel approach to source-level timing estimation with the aim to close the speed-accuracy gap by raising the level of abstraction and improving result reusability. We introduce a concept -elementary operations as distinct parts of source code which enable capturing platform behaviour without having the exact model of the processor pipeline, cache etc. We also present a timing estimation method which relies on elementary operations to craft hardware profiling benchmark and to build application and platform profiles. Experiments show an average estimation error of 5%, with maximum below 16%. ARTICLE HISTORY

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InvadeSIM-A Simulation Framework for Invasive Parallel Programs and Architectures

Roloff

Hannig

Teich

2019

Computer Architecture and Design Methodologies

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Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation

Cited by 8 publications

References 19 publications

Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures

Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures

Elementary operations: a novel concept for source-level timing estimation

InvadeSIM-A Simulation Framework for Invasive Parallel Programs and Architectures

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