Fast area-efficient VLSI adders

Abstract

In this paper, we study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the pro�lem is intimately related to binary addition, the results we obtam lead to the design of area-time efficient VLSI adders.This is a major goal of our work: to design fiery low latency addi tion circuitry that is also area efficient. To this end, we present a new graph representation for prefix computation that leads to the design of a fast, area-efficient binary adder. The new graph is a combination of previously known graph representations for pre fix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, we are able to design VLSI adders having area A = O(nlogn) whose delay time is the lowest possible value, i. e. the fastest possible area-efficient VLSI adder.

Full-custom vs. standard-cell design flow - an adder case study

“…The adders used in the comparison are one 64-bit ordinary ripple-carry adder (RCA) and one 64-bit Han-Carlson tree adder (HCA) [4]. These adder topologies were chosen since they represent two extremes of adder implementations.…”

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“…An example can be analyzed with the first sum bit is calculated by xoring the propagate in the extreme bit (a "1") with the carry-in (a "0"), producing a "1". The second bit is calculated by xoring the propagate in second bit from the MSB (a "0") with first carry out (a "0"), producing a"0" [9]- [10].…”

Design and Implementation of Carry Select Adder without using Multiplexer

“…In digital adder circuits, the speed of addition is limited by the time required for a carry to propagate through the adder. Carry Select Adder (CSA) [6] is one among them and is used to solve the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the final sum.…”