Full-custom vs. standard-cell design flow - an adder case study

Eriksson, Henrik; Larsson-Edefors, Per; Henriksson, Tomas; Svensson, Christer

doi:10.1109/aspdac.2003.1195069

Cited by 12 publications

(8 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We choose an RCA implementation that, scaling for 90 nm technology, consumes approximately the same area as 37 bytes in a single-ported 256-KB tagless cache memory [Eriksson et al 2002] when estimated using CACTI 3.0 [Shivakumar and Jouppi 2001]. This is a conservative estimate for converting adder area to memory area, since the memories we consider for storing branch predictor state have less favorable area characteristics than a 256-KB memory.…”

Section: Misprediction Recoverymentioning

confidence: 99%

See 1 more Smart Citation

Generalizing neural branch prediction

Jiménez

2009

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

Improved branch prediction accuracy is essential to sustaining instruction throughput with today's deep pipelines. Traditional branch predictors exploit correlations between pattern history and branch outcome to predict branches, but there is a stronger and more natural correlation between path history and branch outcome. We explore the potential for exploiting this correlation. We introduce piecewise linear branch prediction, an idealized branch predictor that develops a set of linear functions, one for each program path to the branch to be predicted, that separate predicted taken from predicted not taken branches. Taken together, all of these linear functions form a piecewise linear decision surface. We present a limit study of this predictor showing its potential to greatly improve predictor accuracy.We then introduce a practical implementable branch predictor based on piecewise linear branch prediction. In making our predictor practical, we show how a parameterized version of it unifies the previously distinct concepts of perceptron prediction and path-based neural prediction. Our new branch predictor has implementation costs comparable to current prominent predictors in the literature while significantly improving accuracy. For a deeply pipelined simulated microarchitecture our predictor with a 256-KB hardware budget improves the harmonic mean normalized instructions-per-cycle rate by 8% over both the original path-based neural predictor and 2Bc-gskew. The average misprediction rate is decreased by 16% over the path-based neural predictor and by 22% over 2Bc-gskew.

show abstract

Section: Misprediction Recoverymentioning

confidence: 99%

“…Thus, an n × h shift matrix requires n × h 10-bit adders as well as 10 × n × h latches to store each partial sum. We propose an implementation that would use fast ripple-carry adders (RCA), which provide the best area and delay tradeoff for small bit widths [Eriksson et al 2002].…”

Section: Misprediction Recoverymentioning

confidence: 99%

Generalizing neural branch prediction

Jiménez

2009

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

show abstract

“…Such flows speed up the design phase of medium to high performance integrated circuits (ICs) and are often referred as the key success factor for the rapid growth of integrated systems [1]. One of the reasons for this is the use of a standard library of pre-defined cells, provided by chip or intellectual property (IP) vendors.…”

Section: Introductionmentioning

confidence: 99%

LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries

Moreira

Oliveira

Calazans

et al. 2013

2013 Euromicro Conference on Digital System Design

View full text Add to dashboard Cite

Semi-custom design flows are a key factor for the rapid growth of integrated circuits and systems. They lower design complexity through the use of pre-designed and precharacterized functional components called standard cells, instead of assuming that designers have to draw, place and connect each transistor. In this way, modeling of complex systems is easier. As CMOS technologies evolve into deep submicron nodes, asynchronous techniques gain relevance in the research community, due to their ability to cope with problems that are hard to solve with the synchronous paradigm. However, several specific components required in asynchronous designs are not available in commercial standard cell libraries, which constrains asynchronous design to use approaches close to full-custom ones. This limits modularity and increases design complexity. Thus, one of the possibilities for enabling further advance of the asynchronous paradigm is the availability of asynchronous standard cell libraries. Albeit industrial tools provide reasonable support to asynchronous standard cells physical design, the characterization of these cells using standard tools is usually quite laborious. This work proposes the Library Characterization Environment (LiChEn), an open source tool applicable to automatically characterize typical asynchronous standard cells. The tool managed to successfully characterize a standard cell library with over five hundred asynchronous components.

show abstract

“…It is often challenging to bridge the gap between an analog‐type approach and a digital type approach. Such approach requires integrating several design tools in a single platform to compile and simulate the required circuits …”

Section: Introductionmentioning

confidence: 99%

Integrating multiple state‐of‐the‐art computer‐aided design tools in microelectronics circuit design classes

Abugharbieh

Marar

2019

Comp Applic In Engineering

View full text Add to dashboard Cite

Demand for microelectronics products has seen a recent explosion due to their increased adaption in high-performance data storage, networking, and Internet of Things applications. Not only such products need to provide high performance, they are often integrated in mixed signal environments that include both analog and digital circuits. This has posed a challenge to faculty who teach microelectronics design in senior undergraduate and graduate electrical engineering courses. It is becoming increasingly difficult to upgrade microelectronics curricula, so students are enabled with the proper skills to utilize design tools presently common in the industry. This study provides a mechanism to integrate five state of the art design tools in one single design project. The tools are Custom Compiler, Hewlett Simulation Program with Integrated Circuit, verilog compiler simulator, IC Validator, and Design Complier. Students, through a design project, conduct the design, layout, and simulations of an static random-access memory array. The project utilizes both the full-custom and the semi-custom flows. One full design is created and integrated where students do the design and layout of transistors in specific circuits and generate synthesized circuits automatically from a high-level description language. This study can serve as a resource for senior undergraduate students, graduate students, faculty, and practicing engineers. Finally, it can help electrical engineering programs meet Accreditation Board for Engineering and Technology studentsʼ outcome (k) which is an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice.

show abstract

Full-custom vs. standard-cell design flow - an adder case study

Cited by 12 publications

References 9 publications

Generalizing neural branch prediction

Generalizing neural branch prediction

LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries

Integrating multiple state‐of‐the‐art computer‐aided design tools in microelectronics circuit design classes

Contact Info

Product

Resources

About