Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm

Ryu, Hwa-Sung; Sung, Eun-Taek; Park, Sang Yong; Cho, Je-Kwang; Baek, Dong‐Hyun

doi:10.1109/tvlsi.2016.2627578

Cited by 12 publications

(5 citation statements)

References 9 publications

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“…For a VCO embedded in a PLL, the loop works to lock the VCO to the desired frequency under a given VCO frequency sub-band setting. 27 When the loop settles, the loop filter output voltage Vctrl is compared against two predefined voltage Vhigh and Vlow. If the Vctrl falls outside the range, the PLL is considered unable to lock the VCO properly.…”

Section: Close Loop Automatic Frequency Calibrator (Afc) Designmentioning

confidence: 99%

A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology

Sun

Huang

et al. 2023

Circuit Theory & Apps

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This paper presents a wide‐band charge‐pump phase‐locked loop (CPPLL) with reference spur reduction techniques. To broaden the frequency range without deteriorating phase noise, a 6‐bit capacitor array‐based VCO and an automatic frequency calibrator (AFC) are used. A compact loop filter technique saves the capacitor area and maintains the bandwidth. Also, a novel charge pump with dynamic current matching circuit is proposed to reduce the reference spur of the PLL. The current mismatch is less than 0.22 normalμA (0.16%) over the voltage range from 0.75 to 1.55 V. Fabricated in 0.13 normalμm CMOS technology, the proposed PLL achieves a locking range of 7.6–12.3 GHz (47.2%), with a 25 MHz frequency interval. The PLL consumes 23.3 mA from a 2.5 V supply voltage and occupies a core area of 0.92 mm × 0.72 mm. The reference spur of the proposed PLL is measured to be −81.1 dBc, and in‐band phase noise reaches −110.8 dBc/Hz at 1 MHz offset frequency from the 9.5 GHz carrier frequency.

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Section: Close Loop Automatic Frequency Calibrator (Afc) Designmentioning

confidence: 99%

A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology

Sun

Huang

et al. 2023

Circuit Theory & Apps

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“…In the PLL with conventional AFC, 𝛼 is set to a fixed value to obtain a fixed 𝑀 [13]. The LVTW technology constructs 𝑀 by introducing a scaling factor, 𝜆, which is strongly correlated with the number of AFC control bits, thus adjusting the counting time of the VCO feedback clock.…”

Section: Fast Afc With Lvtwmentioning

confidence: 99%

“…However, the frequency resolution is not affected by this process. Due to the large initial hopping amplitude of the SAR search algorithm [14], it is not necessary that Δ𝑓 approaches the limit of the frequency resolution required by the system (corre- In the PLL with conventional AFC, α is set to a fixed value to obtain a fixed M [13]. The LVTW technology constructs M by introducing a scaling factor, λ, which is strongly correlated with the number of AFC control bits, thus adjusting the counting time of the VCO feedback clock.…”

Section: Fast Afc With Lvtwmentioning

confidence: 99%

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

et al. 2023

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This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window technology and modified multi-modulus dividers (MMD) based on sub-multi-modulus dividers (SMMD) are developed for faster locking, lower jitter, and implementation of multi-protocol data communications applications. The clock generator is fabricated in 0.18 μm CMOS technology. The measured division ratio of the multi-modulus divider ranges from 1.875 to 25, and the output frequency is 46.875~625 MHz. The lock time does not exceed 30 μs, while jitter is less than 500 fs.

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“…Several papers use different algorithms embedded in logic control unit to reduce the calibration time and improve the accuracy of finding suited sub-band. Now, algorithms for finding suited sub-band in common use are linear search [11,13], binary search [9,10,14] and improved binary search [15,16,17]. Many other papers are focused on optimizing frequency comparison circuit to reduce the calibration time and improve fres [18,19,20,21,22].…”

Section: Closed-loop Afc Technique Based On Vctrl Monitoringmentioning

confidence: 99%

An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers

Liu

Gan

2020

IEICE Electron. Express

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A novel VCO auto frequency calibration(AFC) technique is presented in this paper. It provides ultra-fast and high-precision search for an optimum VCO discrete tuning curve among a group of frequency sub-bands in the PLL frequency synthesizer. The calibration circuit consists of a table of frequency (TOF) and a finite state machine (FSM). Asynchronous work of TOF and FSM makes it possible to realize ultrafast and high-precision calibration simultaneously. TOF affords the high-precision of the calibration and FSM with a high-speed clock offers the ultra-fast search. A 2.8G-3.5GHz Fractional-N PLL incorporating the proposed calibration technique is implemented in 55nm CMOS process. The measured calibration time for a 5-bit capacitor bank is 90ns for a frequency resolution of 203KHz. Such small calibration time significantly reduces the effects of calibration time on the total lock time of the PLL.

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Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm

Cited by 12 publications

References 9 publications

A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology

A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers

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