Fast Buffer Count Estimation in 3D IC Floorplanning

Mohapatra, Sucheta; Vendra, Satya K.; Chrzanowska-Jeske, M.

doi:10.1109/tcsii.2020.3007858

Cited by 1 publication

(2 citation statements)

References 11 publications

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“…To deal with the rising complexity of architecture, hierarchical and IPbased components are utilized, making floor planning throughout the VLSI design cycle is increasingly realistic. Researchers have recently discovered the benefits of VLSI floor planning (Vipin 2019;Lin et al 2021a;Mohapatra et al 2020), particularly comprising a large number of chips. The architecture that must be recognized has been put together in floor planning, and specific space should indeed be allocated with different satisfactory limits to bring things close together, thereby reducing the dead space and cost incurred Sivaranjani and Senthil Kumar 2015).…”

Section: Introductionmentioning

confidence: 99%

“…This heuristic approach (Srinivasan and Venkatesan 2021; Guler and Jha 2020) could be used for a global solution. The floor layouts are being shown using a rectangular dissection, and the borders have a rectangle form as well (Teng et al 2018;Chen et al 2018;Lin et al 2021b;Mohapatra et al 2020;Vehring et al 2020). These lines are given vertically or horizontally, and the modules are dumped in a rectangle form to improve the automation process.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization

Pondreti

Kaparapu

2023

International Journal of Swarm Intelligence Research

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Floor planning is indeed an obvious design process in VLSI physical layout since it specifies the dimensions, structure, as well as positions of components upon the chip; in addition, information regarding the overarching silicon area, interlinks, and latency is also provided. VLSI floor planning is an NP-hard issue as the floor plan representations are a crucial component in this process. The intricacy, as well as solution space of the floor plan layout, is influenced by the floorplan visualizations. To tackle the VLSI floor plan challenge, numerous researchers have developed numerous meta-heuristic optimization techniques. The main objective of this work presents a novel multi-objective hybrid optimization method for solving the floor plan optimization issue. Standard DOX and ALO are conceptually combined in the proposed hybrid optimization referred to as Dingo Updated Ant Lion Optimization (DUALO) model. The multi-objectives like wire length, area, and penalty function are taken into consideration.

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