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We propose a new floorplanning approach for TSVbased 3D ICs. A non-negligible area occupied by TSVs, TSVs physical locations and nets-to-TSVs assignment considerably influence chip area, wirelength and delay. TSVs also induce significant thermo-mechanical stress in nearby silicon. The proposed approach addresses the above issues by co-placement of TSVs with circuit blocks, and concurrent nets-to-TSVs assignment for total delay minimization. During the floorplanning process we consider appropriate TSV pitch, Keep-Out-Zone (KOZ) around TSVs and the contribution of TSVs to interconnect delay. Our experimental results show improved solution quality with up to 7% shorter wirelength and an average 8% reduction in the number of TSVs as compared to most recent publications. The total delay reduces between 8% and 36% when delay-aware, instead of wirelength-aware, cost function is used.

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