TSV- and delay-aware 3D-IC floorplanning

Ahmed, Mohamed M.; Mohapatra, Sucheta; Chrzanowska-Jeske, M.

doi:10.1007/s10470-016-0717-1

Cited by 15 publications

(3 citation statements)

References 18 publications

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“…center-to-center distance between adjacent TSVs (pvia) is considered as 23 nm. TSV pitch (pvia) should be equal to or greater than twice the TSV diameter (dtsv) to avoid the misalignment [25]. Based on this concept, the diameter (dtsv) is approximated as 10.5 nm.…”

Section: Tsv Structure and Physical Parametersmentioning

confidence: 99%

An analysis of the eddy effect in through-silicon vias based on Cu and CNT bundles: the impact on crosstalk and power

2021

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The performance of a three dimensional integrated circuit primarily depends on the filler material used in through silicon via (TSV). The mostly used filler material Cu is primarily facing severe reliability issues due to the skin effect and electromugration related problems at high frequencies. Therefore, in recent, single-and multi-walled carbon nanotubes (SWCNT and MWCNT) have been emerged as suitable filler materials in TSV. Additionally, at high frequencies, an electrmagetic force primarly induces to an eddy current that adversely affects the overall performance of a TSV. This paper for the first time demonstrates the impact of eddy current on Cu, bundled SWCNT and MWCNT based TSVs. An accurate RLGC circuit model is proposed by considering the eddy effect at the depletion layer and the silicon substrate region. The equivalent circuit parameters are modelled at 7 nm technology using a three line driver-via-load setup. Using the proposed setup, crosstalk and power disspation are analyzed with and without considering the eddy effect. Irrespective of TSV heights, the MWCNT bundle demonstrates substantially lower crosstalk delay, peak noise and power dissipation in comparison to the Cu and SWCNT bundle based TSVs.

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Section: Tsv Structure and Physical Parametersmentioning

confidence: 99%

An analysis of the eddy effect in through-silicon vias based on Cu and CNT bundles: the impact on crosstalk and power

2021

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show abstract

“…TSV pitch (pvia) should be equal to or greater than twice the TSV diameter (dtsv) to avoid the misalignment [25]. Based on this concept, the diameter (dtsv) is approximated as 10.5 nm.…”

Section: Tsv Structure and Physical Parametersmentioning

confidence: 99%

Analysis of Eddy Effect for Cu and CNT Bundle Based Through-Silicon Vias: Impact on Crosstalk and Power

Sahu¹,

Anand

Majumder³

2021

Preprint

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The performance of a three dimensional integrated circuit primarily depends on the filler material used in through silicon via (TSV). The mostly used filler material Cu is primarily facing severe reliability issues due to the skin effect and electromugration related problems at high frequencies. Therefore, in recent, single- and multi-walled carbon nanotubes (SWCNT and MWCNT) have been emerged as suitable filler materials in TSV. Additionally, at high frequencies, an electrmagetic force primarly induces to an eddy current that adversely affects the overall performance of a TSV. This paper for the first time demonstrates the impact of eddy current on Cu, bundled SWCNT and MWCNT based TSVs. An accurate RLGC circuit model is proposed by considering the eddy effect at the depletion layer and the silicon substrate region. The equivalent circuit parameters are modelled at 7 nm technology using a three line driver-via-load setup. Using the proposed setup, crosstalk and power disspation are analyzed with and without considering the eddy effect. Irrespective of TSV heights, the MWCNT bundle demonstrates substantially lower crosstalk delay, peak noise and power dissipation in comparison to the Cu and SWCNT bundle based TSVs.

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“…In Table 7, we reported only the best delay values obtained on the final floorplan, and respective wirelength and number of TSVs for each circuit. We have used three values for each weight function, α = (0.1, 0.5, 1.0), β = (5,20,50), and γ = (10,50,100). It can Knechtel [16] Tsai [17] Li [18] TSV-DAF be observed that CF2 obviates the need to balance the weights between wirelength and TSVs, resulting in reduced delay in the circuits on an average by 13%.…”

Section: Statistical Analysis Of Cf1mentioning

confidence: 99%

Early Layout Design Exploration in TSV-based 3D Integrated Circuits

Ahmed¹

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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10%-12% compared to wirelength-aware cost function. I would like to express my sincere gratitude to my advisor Prof. Malgorzata Chrzanowska-Jeske for the continuous support of my Ph.D. study and related research, for her patience, motivation, and immense knowledge. Her guidance helped me immensely in all the time of research and writing of this thesis. She was always available for my questions and gave generously for her time and vast knowledge. Besides my advisor, I would like to thank the rest of my thesis committee: Dr. W.

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TSV- and delay-aware 3D-IC floorplanning

Cited by 15 publications

References 18 publications

An analysis of the eddy effect in through-silicon vias based on Cu and CNT bundles: the impact on crosstalk and power

An analysis of the eddy effect in through-silicon vias based on Cu and CNT bundles: the impact on crosstalk and power

Analysis of Eddy Effect for Cu and CNT Bundle Based Through-Silicon Vias: Impact on Crosstalk and Power

Early Layout Design Exploration in TSV-based 3D Integrated Circuits

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