Fast Decimal Floating-Point Division

Nikmehr, Hooman; Phillips, Braden J.; Lim, Cheng‐Chew

doi:10.1109/tvlsi.2006.884047

Cited by 44 publications

(27 citation statements)

References 28 publications

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“…The proposal for radix-10 digit recurrence divison [61] included the most recent developments in the binary digit recurrence algorithms. Similarly, a decimal SRT division [62] was also proposed. A more recent design using functional iteration is based on an internal redundant FMA [63] and uses a special rounding [64] unit.…”

Section: Specific Designsmentioning

confidence: 99%

Decimal Floating Point Number System

Fahmy

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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Section: Specific Designsmentioning

confidence: 99%

Decimal Floating Point Number System

Fahmy

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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“…Nikmehr et al [13] select quotient digits by comparing the truncated residual with limited precision multiples of the divisor. Lang and Nannarelli [14] replace the divisor's multiples by comparative values obtained by a look-up table and decompose the quotient digit into a radix-2 digit and a radix-5 digit in such a way that only five and two times the divisor are required.…”

Section: Decimal Fixed-point Divisionmentioning

confidence: 99%

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Baesler

Voigt

2013

International Journal of Reconfigurable Computing

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Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carrypropagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.

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“…The kn, pl encoding of a binary signed digit in radix-2 position i uses a pair of +2 iweighted bits [9]. Finally, the digit set [29,9] is represented as two 4-bit numbers with oppositely signed weights [17].…”

Section: Representations and Algorithmsmentioning

confidence: 99%

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits

Jaberipur

Parhami

2012

IET Comput. Digit. Tech.

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Most common uses of negatively weighted bits (negabits), normally assuming arithmetic value 21(0) for logical 1(0) state, are as the most significant bit of 2's-complement numbers and negative component in binary signed-digit (BSD) representation. More recently, weighted bit-set (WBS) encoding of generalised digit sets and practice of inverted encoding of negabits (IEN) have allowed for easy handling of any equally weighted mix of negabits and ordinary bits (posibits) via standard arithmetic cells (e.g., half/full adders, compressors, and counters), which are highly optimised for a host of simple and composite figures of merit involving delay, power, and area, and are continually improving due to their wide applicability. In this paper, we aim to promote WBS and IEN as new design concepts for designers of computer arithmetic circuits. We provide a few relevant examples from previously designed logical circuits and redesigns of established circuits such as 2's-complement multipliers and modified booth recoders. Furthermore, we present a modulo-(2 n + 1) multiplier, where partial products are represented in WBS with IEN. We show that by using standard reduction cells, partial products can be reduced to two. The result is then converted, in constant time, to BSD representation and, via simple addition, to final sum.

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Fast Decimal Floating-Point Division

Cited by 44 publications

References 28 publications

Decimal Floating Point Number System

Decimal Floating Point Number System

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits

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