Fast detection of data retention faults and other SRAM cell open defects

Yang, Jixiang; Wang, Baosheng; Wu, Yuejian; Ivanov, A.

doi:10.1109/tcad.2005.852680

Cited by 18 publications

(1 citation statement)

References 29 publications

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“…The resistive defects disturb the charging path of the node or discharging path during the conventional operations of the memory. A small difference in the ground voltages has applied for the write operation to detect the defects in memory [10]. Ensuing operations on the same cells giving higher aging effect and reducing reliability should be condensed [11].…”

Section: Introductionmentioning

confidence: 99%

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

Mali¹,

Tak-Barekar²

2021

JUSST

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The efforts in the semiconductor industry lead to the up-gradation of device size and performance of the devices. Extensive use of cache memory with significant size has become the requirement of most devices, applications, and gadgets. Advanced nanotechnology has resulted in scaled devices and more components with complex circuitry on system-on-chip. The memories are placed incredibly more profound in the die, and memory pins are not accessible readily, leading to more complications in testing the memories. The manufacturing of scaled devices is also a challenging task. A slight variation in doping concentration or process, supply voltage, temperature variations leads to faults in the memory. Advanced technology has increased the possibilities of occurrences of resistive defects in memories. For the smooth operation of systems with high reliability, it is essential to detect all the defects in the memory. In this paper, the detection of resistive defects is proposed at an early stage to increase the life span of the memory cells. Feeble cell detected at an early stage inhibits the more mutilation of the cells and improves memory reliability. An extensive range of defective values is used to analyze the proposed method to cover all positions of the defects in the cell. The proposed method detects the resistive defects with a minimum test time of 81.95μs for 4KB of the memory and contributes a negligible area overhead of 0.77%.

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Section: Introductionmentioning

confidence: 99%