Fast digital foreground gain error calibration for pipelined ADC

Abstract

Here, a fast digital foreground calibration technique to calibrate the gain error in the pipelined analogue-to-digital converter (ADC) is proposed. The technique suggested uses maximum reference value of the ADC along with least mean squares adaptive algorithm to compensate the gain error. It avoids the use of slow but accurate reference ADC, thus saving area, power, and design efforts. The proposed calibration algorithm is implemented in Xilinx Artix-7 FPGA kit to show the effectiveness of the algorithm. After calibration, differential non-linearity improves by 30% and integral non-linearity reduces from values +60/−60 LSB to +0.77/-0.77 LSB. Also, signal to noise and distortion ratio and spurious-free dynamic range improve significantly from 35.9193 and 36.7348 to 75.3619 and 82.2884 dB, respectively, after calibration.

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

“…Obviously, there are many "jumps" at each of the two adjacent subranges. Attention should be paid when V err < 0 because the missing code decreases the ADC performance greatly [26]. Thus, if the V err can be measured and compensated for in a certain way, we can eliminate the nonlinearity caused by capacitor mismatch.…”

An Accurate and Fast Method for Improving ADC Nonlinearity

“…Te nonlinear mismatch error calibration structure was included based on the sinusoidal wave ftting method used in [17,18]. Adaptive least mean square (LMS) algorithms are used for nonlinear error extraction and calibration algorithms for pipeline ADC [19] to compensate for the gain error [20]. Kalman flter (KF) has been proposed as a resolution enhancement method [21].…”