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A 6-bit pipelined analog-to-digital converter (ADC) with low power consumption has been designed. Inverter-based comparators have been used. To provide 6 bits output code 2 stages of pipeline with resolution of 3 bits have been used. In each stage digital-to-analog converter (DAC) and amplifier were implemented without operational amplifiers (Op-amps). Cascode current mirrors with weighted currents have been used to enhance sampling rate. Thus, the results of computer simulation show that ADC achieves 200 Ms/s sampling rate and 1.87 mW power consumption (at ±0,9 V supply voltage). Reported DNL and INL are 0.67 LSB and 1.05 LSB respectively, SNDR and SFDR are 29.7 dB and 33.5 dB respectively, ENOB is 4.64 bit. Inverter-based comparators with reduced influence of manufacturing process and temperature variations were designed. Test chip for 2 bit stage of pipelined ADC was implemented using 180 nm mixed-mode CMOS UMC technology. The stage occupies 0.0026 mm2. Sampling rate is 500 Ms/s, power consumption is approximately. 970 uW

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