Fast FPGA Prototyping based Real-Time Image and Video Processing with High-Level Synthesis

Abstract

Programming in high abstraction level is known by its benefits. It can facilitate the development of digital image and video processing systems. Recently, high-level synthesis (HLS) has played a significant role in developing this field of study. Real time image and video Processing solution needing high throughput rate are often performed in a dedicated hardware such as FPGA. Previous studies relied on traditional design processes called VHDL and Verilog and to synthesize and validate the hardware. These processes are technically complex and time consuming. This paper introduces an alternative novel approach. It uses a Model-Based Design workflow based on HDL Coder (MBD), Vision HDL Toolbox, Simulink and MATLAB for the purpose of accelerating the design of image and video solution. The main purpose of the present paper is to study the complexity of the design development and minimize development time (Time to market: TM) of conventional FPGA design. In this paper, the complexity of the development™ can be reduced by 60% effectively by automatically generating the IP cores and downloading the modeled design through the Xilinx tools and give more advantages of FPGA related to the other devices like ASIC and GPU.

Real Time FPGA Implementation of a High Speed for Video Encryption and Decryption System with High Level Synthesis Tools

“…In order to fulfill the security demands of various application contexts, distinct techniques are necessary for the encryption and decryption system to handle data. Reference [20] developed a customizable encryption system that allowed users to choose their preferred encryption method from a range of options specified in the FPGA configuration file, hence enhancing the flexibility of the system. Reference [21] suggested a hybrid protocol architecture for Short Message Services (SMS) that incorporates AES and Rivest Cipher 4 (RC4) algorithms to enhance the security of smart houses.…”

“…4 operates as a block cipher at the bit level. Each block length is set at 128 bits, whereas the key length can be any value between 128 and 256 bits [20]. Every 128-bit data block is divided into 16 bytes, which are then mapped onto a 4 × 4 array called state.…”

Hardware Acceleration of Video Edge Detection with Hight Level Synthesis on the Xilinx Zynq Platform

“…The MBD technique for FPGAs results from the need to design complex DSP systems which require specific arithmetic units such as the addition-compare-select unit for the Viterbi decoder. These specific computing units require a finer level of FPGA-based circuit optimization [11]. This level of optimization is generally associated with traditional digital design video and image processing system.…”