Fast generation of statistically-based worst-case modeling of on-chip interconnect

Chang, Norman; Kanevsky, Valery; Nakagawa, O.S.; Rahmat, K.; Oh, Soo‐Young

doi:10.1109/iccd.1997.628944

Cited by 16 publications

(14 citation statements)

References 2 publications

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“…Realizing the great importance of process variations, many works have been carried out to model their effect [10,7,2,9,15,1,17,14]. One major objective of these modeling works is to find a reliable estimation on the worst case timing performance induced by process variations, either the worst delay along timing critical paths in timing analysis or the worst skew in a clock network.…”

Section: Introductionmentioning

confidence: 99%

Analytical bound for unwanted clock skew due to wire width variation

Rajaram

Liu

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Under modern VLSI technology, process variations greatly affect circuit performance, especially clock skew which is very timing sensitive. Unwanted skew due to process variation forms a bottleneck preventing further improvement on clock frequency. Impact from intra-chip interconnect variation is becoming remarkable and is difficult to be modeled efficiently due to its distributive nature. Through wire shaping analysis, we establish an analytical bound for the unwanted skew due to wire width variation which is the dominating factor among interconnect variations. Experimental results on benchmark circuits show that this bound is safer, tighter and computationally faster than similar existing approach.

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Section: Introductionmentioning

confidence: 99%

Analytical bound for unwanted clock skew due to wire width variation

Rajaram

Liu

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Other applications that require the solution of a very large number of "similar" configurations are for instance: the generation of capacitance tables used in macro and fullchip parasitic layout extraction [5], [6]; the extraction of capacitance distributions using sampling based techniques as is found in a number of stochastic extraction techniques such as the Monte Carlo or stochastic collocation algorithm [7]; and the generation of parameterized reduced-order models used in timing and noise analysis.…”

Section: Introductionmentioning

confidence: 99%

A capacitance solver for incremental variation-aware extraction

El-Moselhy

Elfadel

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-Lithographic limitations and manufacturing uncertainties are resulting in fabricated shapes on wafer that are topologically equivalent, but geometrically different from the corresponding drawn shapes. While first-order sensitivity information can measure the change in pattern parasitics when the shape variations are small, there is still a need for a high-order algorithm that can extract parasitic variations incrementally in the presence of a large number of simultaneous shape variations. This paper proposes such an algorithm based on the wellknown method of floating random walk (FRW). Specifically, we formalize the notion of random path sharing between several conductors undergoing shape perturbations and use it as a basis of a fast capacitance sensitivity extraction algorithm and a fast incremental variational capacitance extraction algorithm. The efficiency of these algorithms is further improved with a novel FRW method for dealing with layered media. Our numerical examples show a 10X speed up with respect to the boundaryelement method adjoint or finite-difference sensitivity extraction, and more than 560X speed up with respect to a non-incremental FRW method for a high-order variational extraction.

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“…In the first phase, the 3-sigma values of capacitance, resistance, and partial derivatives of capacitances with respect to selected interconnect process parameters are generated in batch-mode computation as part of an enhanced version of HIVE [2], which is a parameterized interconnect model generator and library for R and C, and the Derivative HIVE Generator. Most of time is spent in derivative calculation in this phase.…”

Section: Statistical Modeling and Differentiating Of Fcap Codesmentioning

confidence: 99%

“…We have developed a methodology [2] for obtaining 3-sigma R (resistance), C (capacitance), crosstalk, and delay given variations in interconnect-related process parameters. This methodology uses FCAP2 and FCAP3 [3] (Fast Capacitance Extraction 2-D and 3-D simulators, respectively) that have been developed at Hewlett Packard Laboratory to study parasitic electrical effects of interconnects and devices.…”

Section: Introductionmentioning

confidence: 99%

Fast statistical-based interconnect modeling using automatic differentiation

Roh

Bischof²,

Chang

et al.

1999 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD'99 (IEEE Cat. No.99TH8387)

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Automatic differentiation is a technique for computing derivatives accurately and eficiently with minimal human effort. We employed this technique to generate derivative information of FCAP2/3 programs that simulate the parasitic effects of interconnects. This derivative information is used in the statistical modeling of worst-case interconnect delays and on-chip crosstalks. The ADIC (Automatic Differentiation in C) tool generated new versions of FCAP2 and FCAP3 programs that compute both the original results and the derivative information.We report on the use of automatic differentiation and divided difference approaches for computing derivatives for FCAP3 programs. The results show that ADIC-generated code computes derivatives more accurately, more robustly, and faster than the divided difference approach.

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Fast generation of statistically-based worst-case modeling of on-chip interconnect

Cited by 16 publications

References 2 publications

Analytical bound for unwanted clock skew due to wire width variation

Analytical bound for unwanted clock skew due to wire width variation

A capacitance solver for incremental variation-aware extraction

Fast statistical-based interconnect modeling using automatic differentiation

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