2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2015
DOI: 10.1109/vlsi-soc.2015.7314436
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Fast global interconnnect driven 3D floorplanning

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Cited by 5 publications
(1 citation statement)
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“…For 3D chip stacks, the module arrangement is interdependent across the whole stack, rendering 3D floorplanning much more complex than 2D floorplanning. 2 Existing floorplanning methodologies already address key challenges such as thermal management [27,[34][35][36], co-arrangement of modules and TSVs [59] or planning of system-level buses [27,36,60]. Still, 3D floorplanning is a highly technology-dependent and iterative process-fast, accurate and configurable design evaluation is currently targeted but still to be enhanced [61,62].…”
Section: Partitioning and Floorplanningmentioning
confidence: 99%
“…For 3D chip stacks, the module arrangement is interdependent across the whole stack, rendering 3D floorplanning much more complex than 2D floorplanning. 2 Existing floorplanning methodologies already address key challenges such as thermal management [27,[34][35][36], co-arrangement of modules and TSVs [59] or planning of system-level buses [27,36,60]. Still, 3D floorplanning is a highly technology-dependent and iterative process-fast, accurate and configurable design evaluation is currently targeted but still to be enhanced [61,62].…”
Section: Partitioning and Floorplanningmentioning
confidence: 99%