Fast hierarchical multi-level fault simulation of sequential circuits with switch-level accuracy

Meyer, W.; Camposano, Raúl

doi:10.1145/157485.165011

Cited by 24 publications

(10 citation statements)

References 14 publications

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“…Work in [121] simulates transistor-level defects using SPICE and abstracts the resulting behavior to logic level by using a new algebra. Work in [122,123] uses mixed-level fault simulation to simulate a defect more accurately while maintaining a tolerable simulation speed. Unfortunately, the work in [43,[117][118][119] depends on simulating the entire circuit at the transistor level and therefore is not scalable.…”

Section: Prior Workmentioning

confidence: 99%

“…Unfortunately, the work in [43,[117][118][119] depends on simulating the entire circuit at the transistor level and therefore is not scalable. The work in [121][122][123], while scalable, does not consider layout and therefore sacrifices accuracy. In addition, the variety of defects considered in [121][122][123] is quite limited.…”

Section: Prior Workmentioning

confidence: 99%

“…The work in [121][122][123], while scalable, does not consider layout and therefore sacrifices accuracy. In addition, the variety of defects considered in [121][122][123] is quite limited.…”

Section: Prior Workmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

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Section: Prior Workmentioning

confidence: 99%

Section: Prior Workmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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“…Approaches to fault simulation include basic gate-level algorithms [1] and several hybrid methods. These methods either combine basic methods (like PROOFS [20]), or they use different levels of abstraction to speed up the simulation process [13][27] [18]. Although these methods are faster than the traditional gate-level methods, they are still not scalable.…”

Section: Introductionmentioning

confidence: 99%

FALCON: Rapid statistical fault coverage estimation for complex designs

Mirkhani

Abraham

et al. 2012

2012 IEEE International Test Conference

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Abstract-FALCON (FAst fauLt COverage estimatioN) is a scalable method for fault grading which uses local fault simulations to estimate the fault coverage of a large system. The generality of this method makes it applicable for any modular design. Our analysis shows that the run time of our algorithm is related to the number of gates and the number of IOs in a module, while fault simulation run time is related to the total number of gates in the system. We have measured fault coverage for OR1200 and IVM processors and compared the results with fault simulation performed by a commercial tool. We have also compared our results with fault sampling. Our results show that for large designs FALCON works faster (one order of magnitude) compared to fault simulation. It also has smaller error rate compared to fault sampling when the size of design under test grows.

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“…Blocks which are not to be fault-simulated, or do not have a gate-level representation, can thus be modeled at a higher level of abstraction. More recent developments, like FEHSIM [8], use enhanced scheduling techniques to dynamically switch between different levels of abstraction such as to maximize speed without losing accuracy.…”

Section: Introductionmentioning

confidence: 99%

Software Accelerated Functional Fault Simulation for Data-Path Architectures

Kassab

1995

32nd Design Automation Conference

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-This paper demonstrates how fault simulation of building blocks found in data-path architectures can be performed extremely efficiently and accurately by taking advantage of their simple functional models and structural regularity. This technique can be used to accelerate the simulation of those blocks in virtually any fault simulation environment, resulting in fault simulation algorithms that can perform fault grading in a very demanding BIST environment.

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Fast hierarchical multi-level fault simulation of sequential circuits with switch-level accuracy

Cited by 24 publications

References 14 publications

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

FALCON: Rapid statistical fault coverage estimation for complex designs

Software Accelerated Functional Fault Simulation for Data-Path Architectures

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