Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Abstract

In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

DREAMS: DFM Rule EvAluation using Manufactured Silicon

“…Failures due to other sources (e.g., random-spot contaminations, systematic defects, etc.) are assumed to have been already removed from the population of N failed chips using existing approaches [17][18][19]. This means that the failed-chip population can be distributed among the K rules.…”

An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model

“…One important step of fault diagnosis is to generate a suitable set of patterns that can be applied to the chips via automatic test equipment (ATE) such that proper diagnosis information of the chips can be collected and analyzed. Figure 1(a) shows a typical volume diagnosis flow [2][3][4][5][6][7][8][9][10]. A set of test patterns (TP) generated by an ATPG tool is applied to the chips via automatic test equipment (ATE) to produce a failure log (FL), i.e., the output responses of failing patterns.…”

“…The FL is then analyzed by a diagnosis analysis tool to derive a list of candidates (CD) for the PFA process. To reduce the number of fault candidates and increase the hit ratio of PFA, various techniques have been employed in the diagnosis analysis tool, including POIROT [2], single location at-a-time (SLAT) [3], diagnosis-assisted adaptive test (DAT) [4], machine-learning based methods [5][6], layout-aware diagnosis tools [7][8], design-partition analysis [9] and fault-rescoring tool [10]. Since only the original test pattern set is used in this flow, no extra patterns are needed.…”

An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults

“…One important step of fault diagnosis is to generate a suitable set of patterns that can be applied to the chips via automatic test equipment (ATE) such that proper diagnosis information of the chips can be collected and analyzed. Figure 1(a) shows a typical volume diagnosis flow [2][3][4][5][6][7][8][9][10]. A set of test patterns (TP) generated by an ATPG tool is applied to the chips via an automatic test equipment (ATE) to produce a failure log (FL), i.e., the output responses of failing patterns.…”

“…The FL is then analyzed by a diagnosis analysis tool to derive a list of candidates (CD) for the PFA process. To reduce the number of fault candidates and increase the hit ratio of PFA, various techniques have been employed in the diagnosis analysis tool [2][3][4][5][6][7][8][9][10]. However, since only the original test pattern set is used in this flow, it is often inadequate to filter out some incorrect candidates.…”