Fast IR drop estimation with machine learning

Fouda

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

et al. 2023

Recently, ReRAM-based hardware accelerators showed unprecedented performance compared the digital accelerators. Technology scaling causes an inevitable increase in interconnect wire resistance, which leads to IR drops that could limit the performance of ReRAM-based accelerators. These IR drops deteriorate the signal integrity and quality especially in the Crossbar structures which are used to build high density ReRAMs. Hence, finding a software solution that can predict the effect of IR drop without involving expensive hardware or SPICE simulations, is very desirable. In this paper, we propose two neural networks models to predict the impact of the IR drop problem. These models are uded to evaluate the performance of the different deep neural networks (DNNs) models including binary and quantized neural networks showing similar performance (i.e., recognition accuracy) to the golden validation (i.e., SPICEbased DNN validation). In addition, these predication models are incorporated into DNNs training framework to efficiently retrain the DNN models and bridge the accuracy drop. To further enhance the validation accuracy, we propose incremental training methods. The DNN validation results, done through SPICE simulations, show very high improvement in performance close to the baseline performance, which demonstrates the efficacy of the proposed method even with challenging datasets such as CIFAR10 and SVHN.

Section: Related Workmentioning

confidence: 99%

Offline Training-Based Mitigation of IR Drop for ReRAM-Based Deep Neural Network Accelerators

Fouda

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

et al. 2023

IEICE Trans. Inf. & Syst.

“…Nevertheless, [13] considers both location information and PDN structure to provide a highquality IR-drop profile and reveal severe regional IR-drop without incurring high computation overhead. Recently, there have been machine-learning-based methods targeting dynamic IR-drop estimation [14], [16], [19]. They can estimate IR-drop quickly and view IR-drop as a constraint to optimize test patterns or speedup engineer change order (ECO) iterations.…”

Section: Dynamic Ir-drop Estimationmentioning

confidence: 99%

GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting

SHI,

HOLST,

WEN

2023

High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems:(1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.

“…Additionally, it might be measured after silicon verification. Hence using machine learning techniques, a new method for estimating IR drop during chip design is reported [9] and the traditional approach of using simulation-based commercial tools is too time-consuming and may not be accurate. This method uses a neural network to estimate IR drop, which can significantly reduce the time required for estimation and can provide accurate results even with limited data, making it suitable for early-stage design.…”

Section: Introductionmentioning

confidence: 99%

Analysis of IR Drop for Robust Power Grid of Semiconductor Chip Design: A Review

Fatima

Chandel

2023

ITM Web Conf.

Modern semiconductor industry has a major focus on die size reduction and favours the usage of multiple metal layers to increase gross margins. High congestion and voltage or IR drop challenges result from designs with higher and lower core utilisations. Owing to this issue, one of the major difficulties in large silicon-on-chip (SoC) design is the implementation of a power grid design. It’s essential to correctly analyze IR drops to guarantee the reliability of the power grid. This paper presents a comprehensive review approach for the analysis of IR drop for robust power grid design in semiconductor chips. The necessity of the vector-based dynamic analysis and the drawbacks of the vector-less analysis have been addressed. The various techniques used to mitigate IR drop effects, including power grid modeling techniques, use of decoupling capacitors, and voltage drop analysis are explored. The review concludes by identifying the most promising techniques for robust power grid design in semiconductor chips and providing recommendations for future research. The simulations are carried out using ANSYS RedHawk, and the analysis findings are achieved using FinFET technology.