Fast low-power full-adders based on bridge style minority function and multiplexer for nanoscale

Ebrahimi, Seyyed Ashkan; Keshavarzian, Peiman

doi:10.1080/00207217.2012.720948

Cited by 18 publications

(6 citation statements)

References 26 publications

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“…MAJ and MIN logic gates as significant elements of much more complex logic systems (e.g., full‐adder and full‐subtractor etc. [ 38–40 ] ), return true (“1”) for MAJ and false (“0”) for MIN, only when more than half of inputs are true (“1”). Based on TSD mode and the universal dual‐signal transducer (H‐AgNCs), 3‐bit MAJ^MIN logic systems were further established.…”

Section: Figurementioning

confidence: 99%

Illuminating Diverse Concomitant DNA Logic Gates and Concatenated Circuits with Hairpin DNA‐Templated Silver Nanoclusters as Universal Dual‐Output Generators

Zhou

Fan

et al. 2020

Advanced Materials

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issues which should be taken seriously. Plenty of logic devices with multi-output signals are implemented by the aid of covalently labeled reporters (e.g., dye or redox), which cause time wastage and high cost. [10][11][12][13][14][15][16][17] In order to generate more than one output signal, it is ineluctable to introduce many other types of substances (e.g., different dyes and unstable hydrogen peroxide), [18,19] which increase complexity of a logic platform and are much detrimental to the repeatability and assembly of different logic systems. In addition, sequence redesign is required for construction of different logic gates, which leads to high cost and low efficiency. Hence, to explore a simple and noncovalent logic platform in a cost-effective manner is urgently demanded.Aimed at surmounting these drawbacks, new DNA-based logic systems should be considered. DNA-templated silver nanoclusters (AgNCs) with excellent fluorescence properties have attracted wide research interests in the field of fabrication of logic devices, [20][21][22][23][24] due to remarkable merits, such as low cost, tunable emission wavelength, ease of preparation, and convenience of utilization in DNA reaction circuits, and noncovalent (so called label-free) and distinctive logic systems could be designed. [21,22,25,26] Recently, a concept of "DNA Janus Logic Pair", also named as "Contrary Logic Pair", was proposed, [18,27] in which two contrary logic gates (positive and negative gates) were obtained via the same one-time reaction, resulting in significant improvement of computing efficiency. However, systematic complexity remains as a constraining factor for effective implementation and integration of DNA-based logic systems. In this study, diverse concomitant contrary logic gates (CCLGs), such as INHIBIT (INH)^IMPLICATION (IMP), XOR^XNOR and MAJORITY (MAJ)^MINORITY (MIN) ("^" stands for "concomitant and contrary"), and extended concatenated logic circuits (e.g., 4-input MAJ||MIN-INH||IMP, "||" stands for "parallel") with specific functions (e.g., parity generator (Pg) and checker (Pc)) were constructed, by utilization of one novel type of hairpin DNA-templated AgNCs (H-AgNCs) as the universal dualfluorescence signal transducer, and based on the mechanism of DNA hybridization and toehold-mediated strand displacement (TSD). Each pair of CCLGs was achieved via the same DNA (YES^NOT, OR^NOR, INHIBIT^IMPLICATION, XOR^XNOR, and MAJORITY^MINORITY) and extended concatenated logic circuits are presented and some of them perform specific functions, such as parity generators and checkers. The introduction of H-AgNCs as noncovalent signal reporters avoids tedious and high-cost labeling procedures. Of note, the concomitant feature of CCLGs attributed to the dual-emitter AgNCs conduces to reducing the time and cost to devise multiple logic gates. As compared to previous ones, this design eliminates numerous substances (e.g., organic dyes) and unstable components (hydrogen peroxide), which not only decreases the complexity of logic performs and impr...

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Section: Figurementioning

confidence: 99%

Illuminating Diverse Concomitant DNA Logic Gates and Concatenated Circuits with Hairpin DNA‐Templated Silver Nanoclusters as Universal Dual‐Output Generators

Zhou

Fan

et al. 2020

Advanced Materials

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“…However, CSLA suffers from the serious disadvantages of increased area and power usage, thus making it unsuitable for portable gadgets. This has attracted lot of research suggesting improvements for the efficient usage of area in CSLA while maintaining its speed for low-power applications (Ceiang and Hsiao, 1998;Kim and Kim, 2001;He et al, 2005;Ramkumar et al, 2010;Ramkumar and Kittur, 2012;Wey et al, 2012;Ebrahimi and Keshavarzian, 2013;Devi et al, 2010). In this section, this paper discusses in detail the existing CSLA architectures.…”

Section: Existing Architecturementioning

confidence: 99%

“…This impacts the adder's importance in almost all digital applications, including digital signal and image processing, digital communication and general-purpose processors. Hence, this paves the way for the development in adders, which results in improved speed, area and power while implementing in hardware (Ceiang and Hsiao, 1998;Kim and Kim, 2001;He et al, 2005;Ramkumar et al, 2010;Ramkumar and Kittur, 2012;Wey et al, 2012;Ebrahimi and Keshavarzian, 2013;Devi et al, 2010). This includes ripple carry adders (RCAs), carry look-ahead adders (CLAs), carry save adders (CSAs) and carry select adders (CSLAs).…”

Section: Introductionmentioning

confidence: 99%

An efficient architecture for carry select adder

Vaithiyanathan

2017

WJE

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Purpose Adders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, consequently, reduce power. Among these, modified CSLAs show a significant improvement, as they utilize a binary excess-1 code (BEC) to replace the add-one circuit. Design/methodology/approach This paper presents further enhancement in the modified CSLA by proposing a decision-based CSLA, which activates BEC on demand. This leads to reduced switching activity. The performance of the proposal is done by analyzing and comparing it with different adders. The comparison is done on the basis of three performance parameters: area, speed and power consumption. This is done by implementing the architecture on Xilinx Virtex5 XC5VLX30 in Verilog environment and is synthesized using Cadence® RTL Compiler® using TSMC 180-nm CMOS cell library. Findings Optimization of power, area and increasing the speed of operation are the three main areas of research in very-large-scale integration (VLSI) design for portable devices. As adders are the most fundamental units for any VLSI design, optimization at the adder level has a huge impact on the overall circuit. The modified CSLA has a BEC which continuously switches irrespective of the previous carry bit generated. The unwanted switching results in excess power consumption while also introducing additional delay. Hence, the author has proposed a decider circuit to avoid this excess switching activity. This allows switching of the BEC only when a previous carry is generated. The modified CSLA is based on the ripple carry adder, while the decider-based CSLA utilizes a carry look-ahead adder. This makes a decider-based CSLA faster while utilizing less area and power consumption when compared to the modified CSLA. Originality/value The efficiency of the proposed decider-based CSLA has been verified using Cadence RTL Compiler using TSMC 180-nm CMOS cell library and has been found to have 17 per cent power and 11.57 per cent area optimization when compared to the modified CSLA, while maintaining operating frequency.

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“…The limitations in CMOS technology such as high lithography, short channel effects, and power consumption encouraged scientists to think about alternatives. Many nanotechnologies were emerged to overcomes these limitations such as Single Electron Transistor [1,2], Carbon Nanotube Field-Effect Transistor [3][4][5][6][7], FinFET [8][9][10] and Quantum-dot Cellular Automata (QCA). QCA technology was introduced for the first time by Lent et al in 1993 [11] and it is reliability was studied in [12].…”

Section: Introductionmentioning

confidence: 99%

Novel Memory Structures in QCA Nano Technology

Majeed

Alkaldy²,

Zainal³

et al. 2020

IJEEE

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Quantum-dot Cellular Automata (QCA) is a new emerging technology for designing electronic circuits in nanoscale. QCA technology comes to overcome the CMOS limitation and to be a good alternative as it can work in ultra-high-speed. QCA brought researchers attention due to many features such as low power consumption, small feature size in addition to high frequency. Designing circuits in QCA technology with minimum costs such as cells count and the area is very important. This paper presents novel structures of D-latch and D-Flip Flop with the lower area and cell count. The proposed Flip-Flop has SET and RESET ability. The proposed latch and Flip-Flop have lower complexity compared with counterparts in terms of cell counts by 32% and 26% respectively. The proposed circuits are designed and simulated in QCADesigner software.

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Fast low-power full-adders based on bridge style minority function and multiplexer for nanoscale

Cited by 18 publications

References 26 publications

Illuminating Diverse Concomitant DNA Logic Gates and Concatenated Circuits with Hairpin DNA‐Templated Silver Nanoclusters as Universal Dual‐Output Generators

Illuminating Diverse Concomitant DNA Logic Gates and Concatenated Circuits with Hairpin DNA‐Templated Silver Nanoclusters as Universal Dual‐Output Generators

An efficient architecture for carry select adder

Novel Memory Structures in QCA Nano Technology

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