Fast modulo 2&lt;sup&gt;n&lt;/sup&gt;&amp;#x2212;1 and 2&lt;sup&gt;n&lt;/sup&gt;&amp;#x003B;1 adder using carry-chain on FPGA

Didier, Laurent-Stéphane; Jaulmes, Luc

doi:10.1109/acssc.2013.6810475

Cited by 4 publications

(4 citation statements)

References 18 publications

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“…The proposed PPA design giving a 22.6% in ADP saving and 24.2% in EDP compared to the PPA designs based on Algorithm-2 (H.T. Vergos et al,2018, Patel R.A. et al,2007, S. Mathew et al, 2003, L.S. Didier et al,2013, B. Patel et al,2018 which is leading with the existing Parallel Prefix Adder designs.…”

Section: Table 3 Synthesis Results Of Parallel Prefix Adder Designmentioning

confidence: 82%

Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder

Patel¹,

Kanungo²

2022

JER is an international, peer-reviewed journal that publishes f

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Residue Number System has to carry free operation and its various applications like digital signal processing, multimedia, security purpose, and medical perception. Removes of the redundant logic operation require the group carry selection logic which is dependent on Parallel Prefix Adder design. Therefore the logic operation of the preprocessing unit of PPA is simplified form to save logic resources. This modified parallel prefix adder consumes less area as compared to the existing design. In this paper, we propose the parallel architecture based on a parallel prefix tree is helpful for computation at higher speed operation. The reported design consumes 24.1% more area and 26.4% more power compare to THE proposed parallel prefix adder design. The proposed PPA design using modified carry computation algorithm and reported design used diminished-1 modulo 2n+1 adder structure is presented. A presented modulo adder design using the proposed parallel prefix adder and improved carry computation used in the previously proposed design. The proposed diminished-1 modulo (2n +1) adder design shows a 24.5% saving in area-delay-product (ADP).

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Section: Table 3 Synthesis Results Of Parallel Prefix Adder Designmentioning

confidence: 82%

Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder

Patel¹,

Kanungo²

2022

JER is an international, peer-reviewed journal that publishes f

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“…Similarly, in [19–21] researchers have focused to improve the design efficiency of PPA. However, the adder structures suggested for CLA and PPA [13–21] are efficient in terms of delay but they occupy a large area and consume more energy, whereas the structure suggested for RCA in [9, 12] involves less area and energy with higher delay. Therefore, the carry select scheme‐based adder [22] has been suggested to achieve the performance between RCA and CLA.…”

Section: Introductionmentioning

confidence: 99%

“…A Manchaster carry chain‐based 4‐bit CLA module [13] and an 8‐bit module [14] are developed for the efficient implementation of large‐size CLA adders. Few PPAs are suggested [15–21]. In [15], Kogg and Stone have given the tree prefix algorithm to compute the intermediate carries parallelly in the tree structure and these carries are used to compute the final sum.…”

Section: Introductionmentioning

confidence: 99%

“…Further, a sparse parallel prefix carry computation method has been suggested in [18], where the group carry selection‐based approach is used to reduce the hardware complexity of the PPA design. Similarly, in [19–21] researchers have focused to improve the design efficiency of PPA. However, the adder structures suggested for CLA and PPA [13–21] are efficient in terms of delay but they occupy a large area and consume more energy, whereas the structure suggested for RCA in [9, 12] involves less area and energy with higher delay.…”

Section: Introductionmentioning

confidence: 99%

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Area–delay and energy efficient multi‐operand binary tree adder

Patel

Singhal

2020

IET Circuits, Devices & Systems

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Here, the critical path of ripple carry adder (RCA)-based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing RCA. Using this RCA design, the BTA structure is proposed. The synthesis result reveals that the proposed 32-operand BTA provides the saving of 22.5% in area-delay product and 28.7% in energy-delay product over the recent Wallace tree adder which is the best among available multi-operand adders. The authors have also applied the proposed BTA in the recent multiplier designs to evaluate its performance. The synthesis result shows that the performance of multiplier designs improved significantly due to the use of proposed BTA. Therefore, the proposed BTA design can be a better choice to develop the area, delay and energy efficient digital systems for signal and image processing applications.

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