Fast modulo scheduler utilizing patternized routes for coarse-grained reconfigurable architectures

Abstract

Coarse-Grained Reconfigurable Architectures (CGRAs) present a potential of high compute throughput with energy efficiency. A CGRA consists of an array of Functional Units (FUs), which communicate with each other through an interconnect network containing transmission nodes and register files. To achieve high performance from the software solutions mapped onto CGRAs, modulo scheduling of loops is generally employed. One of the key challenges in modulo scheduling for CGRAs is to explicitly handle routings of operands from a source to a destination operations through various routing resources. Existing modulo schedulers for CGRAs are slow because finding a valid routing is generally a searching problem over a large space, even with the guidance of well-defined cost metrics. Applications in traditional embedded multimedia domains are regarded as relatively tolerant to a slow compile time in exchange for a high-quality solution. However, many rapidly growing domains of applications, such as 3D graphics, require a fast compilation. Entrances of CGRAs to these domains have been blocked mainly due to their long compile time. We attack this problem by utilizing patternized routes, for which resources and time slots for a success can be estimated in advance when a source operation is placed. By conservatively reserving predefined resources at predefined time slots, future routings originating from the source operation are guaranteed. Experiments on a real-world 3D graphics benchmark suite show that our scheduler improves the compile time up to 6,000 times while achieving an average 70% throughputs of the state-of-the-art CGRA modulo scheduler, the Edge-centric Modulo Scheduler (EMS).

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

“…However, it is not easy to map a computation-intensive Data Flow Graph (DFG) onto a Reconfigurable Cell Array (RCA), because there are many constraints. In previous studies, researchers have presented a wide range of mapping algorithms based on a variety of CGRAs [2][3][4][5][6][7][8][9][10][11][12][13][14] . Yoon et al [2] proposed the spatial mapping algorithm, known as Split-Push Kernel Mapping (SPKM), to map several applications onto resource sharing and pipelining architecture.…”

“…Lee et al [8] and Jo et al [9] introduced approaches for supporting floating-point operations for CGRAs. Kim et al [10] proposed a fast modulo routing scheduling technique for mapping 3D graphics benchmarks onto CGRAs, which improved the compilation speed. Level-Breadth-Mapping (LBM) partitions the nodes by level.…”

Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures

“…As the basic blocks in a CDFG are represented as DFGs, any of the known DFG mapping onto CGRA [5,16,3,9] can be applied to map the basic blocks. Mapping of the basic blocks is done independently, since execution of basic blocks are mutually exclusive.…”