Fast Monolithic 8-2 Adder Compressor Circuit

Abstract

Adder compressor architectures have been widely used in multipliers and have recently achieved improvements over conventional approaches in the computation of multiple modules, such as transform blocks, in the context of video coding. This paper reviews four different state-of-the-art 8-2 adder compressor architectures and proposes a novel one. A 65 nm commercial standard cell library was used to synthesize the compressors. The results show that, as a consequence of a shorter critical path, our circuit presented significant improvements regarding maximum operational frequency, while still maintaining similar results for power dissipation. Our circuit also managed to achieve a smaller circuit area, as a result of a more straightforward net interconnection.