Fast parallel CRC algorithm and implementation on a configurable processor

Ji, Houxiang; Killian, Earl

doi:10.1109/icc.2002.997161

Cited by 25 publications

(24 citation statements)

References 8 publications

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“…They differ from our implementation in that they require separate implementation for every generator polynomial, while our circuits support variable number of CRC standards with only one implementation. Our fully-adaptable Slicing-by-16 (M=128) implementation is 41x faster than [8] soft-coded design with 32 bit CRC and 14.5x faster than hard-coded design. Unfortunately, the reconfiguration time and area utilization are not provided.…”

Section: Comparison To Related Workmentioning

confidence: 94%

“…There are only two adaptable hardware implementa- tions with limited support for a number of generator polynomials [8], [9]. They differ from our implementation in that they require separate implementation for every generator polynomial, while our circuits support variable number of CRC standards with only one implementation.…”

Section: Comparison To Related Workmentioning

confidence: 99%

“…We found only two other hardware implementations [8], [9] that can support very limited number of generator polynomials. The re-generation in [8] is achieved with Galois Field Multiplication and Accumulation (GFMAC) with soft-coded and hard-coded generator polynomials. Soft-coded implementation is much slower than fixed hard-coded counterpart.…”

Section: Related Workmentioning

confidence: 99%

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High-Speed Fully-Adaptable CRC Accelerators

Akagić

Amano

2013

IEICE Trans. Inf. & Syst.

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Amila AKAGIC†a) , Nonmember and Hideharu AMANO †b) , Member SUMMARY Cyclic Redundancy Check (CRC) is a well known error detection scheme used to detect corruption of digital content in digital networks and storage devices. Since it is a compute-intensive process which adversely affects performance, hardware acceleration using FPGAs has been tried and satisfactory performance has been achieved. However, recent extended usage of networks and storage systems require various correction capabilities for various CRC standards. Traditional hardware designs based on the LFSR (Linear Feedback Shift Register) tend to have fixed structure without such flexibility. Here, fully-adaptable CRC accelerator based on a table-based algorithm is proposed. The table-based algorithm is a flexible method commonly used in software implementations. It has been rarely implemented with the hardware, since it is believed that the operational speed is not enough. However, by using pipelined structure and efficient use of memory modules in FPGAs, it appeared that the table-based fixed CRC accelerators achieved better performance than traditional implementation. Based on the implementation, fully-adaptable CRC accelerator which eliminate the need for many non-adaptable CRC implementations is proposed. The accelerator has ability to process arbitrary number of input data and generates CRC for any known CRC standard, up to 65 bits of generator polynomial, during run-time. Further, we modify Table generation algorithm in order to decrease its space complexity from O(nm) to O(n). On Xilinx Virtex 6 LX550T board, the fully-adaptable accelerators occupy between 1 to 2% area to produce maximum of 289.8 Gbps at 283.1 MHz if BRAM is deployed, or between 1.6 -14% of area for 418 Gbps at 408.9 MHz if tables are implemented in logic. Proposed architecture enables further expansion of throughput by increasing a number of input bits M processed at a time.

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Section: Comparison To Related Workmentioning

confidence: 94%

Section: Comparison To Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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High-Speed Fully-Adaptable CRC Accelerators

Akagić

Amano

2013

IEICE Trans. Inf. & Syst.

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“…Glaise [10] used the theory of Galois Fields GF(2m) and employed a GF multiplier for optimized parallel CRC calculation [25]. By inspecting the operations of the single-input LFSR, Pei [26], derived the state transition equation for the parallel CRC circuit by merging a number of the shift and modulo-2 (XOR) operations together within a single clock cycle [27]. Also some attempts of fast CRC computation, which is based on the observation that only a small portion residing in the beginning of an Ethernet frame is changed during the hopes for updating the relevant source and destination address over network.…”

Section: 13mentioning

confidence: 99%

Configurable CRC Error Detection Model for Performance Analysis of Polynomial: Case Study for the 32-Bits Ethernet Protocol

Gad

Naik

2015

Lecture Notes in Computer Science

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Abstract. Almost every form of digital information exchange can introduce communication errors. In order to overcome the inherent inaccuracy of information transmission, a few methods for error detection and correction have been developed. Cyclic Redundancy check Codes (CRCs) are used in embedded networks for effective error detection. Paper discusses the development of the simulation model for the configurable CRC-polynomials performance analysis over Binary Symmetric Channels (BSCs). This paper presents a novel model which can be used to investigate several classes of CRC polynomials codes with 'n' parity bits varying from '1' to '64'. It also discuss the hardware implementation on Altera's FPGA Stratix II GX device 'EP2SGX90FF1508C3' for CRC-32 'IEEE-802' and suggest the indirect methodology of CRC-performance using Packet Error Rate (PER) parameter using Altera TSE MegaCore function that supports 10/100/1000 Mbps Ethernet over 1000Base-LX physical media. It is proposed to search good CRC codes of 32, 40 and 64 bit and studying performance for maximum payload over Ethernet protocol.

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“…They showed the efficiency of their algorithm for 10G Ethernet as well as ATM. Ji, et al [16] presented a method based on Galois Fields multiplication and accumulation operations for CRC calculation. This method can gain unlimited speedup over serial methods and lookup-driven methods but increase area due to the need for GFMAC (Galois Field Multiplication and Accumulation) modules.…”

Section: Related Workmentioning

confidence: 99%