Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs

Abstract

We present a placement-aware 3-D floorplanning algorithm that considers 3-D-placement of logic gates inside modules for wirelength minimization. It allows designers to introduce and evaluate an assignment of vertically-aligned parts of the same module to different device layers. A set of vertical constraints is derived on sequence pairs of different device layers that reduces the solution space, and a fast packing algorithm with vertical constraints enables quick floorplan evaluation. Experimental results on MCNC and GSRC benchmarks show that our algorithm can generate a good floorplanning solution with reduced wirelength inside modules and optimized footprint area while controlling the number of vias. Compared to the existing state-of-the-art 3-D floorplanning algorithms, our tool reduces the system level total wirelength by 9.8%.

TSV capacitance aware 3-D floorplanning

“…We modified the 3D-FVC floorplanner presented in [9] to perform TSV island packing together with packing of circuits' blocks. 3D FVC uses Sequence Pair (SP) representation and is based on Evolutionary Algorithm (EA).…”

Power efficiency of 3D vs 2D ICs

“…There are various approached for 3-D floorplanning that consider TSV locations proposed in the literature [6]- [9]. Some of the early approaches [6] treated TSVs as points ignoring the impact of TSV sizes on area and wirelength.…”

“…Some of the early approaches [6] treated TSVs as points ignoring the impact of TSV sizes on area and wirelength. Tsai et al [7] considered TSVs as cells, and observed the impact on the area and wirelength of the floorplan but did not discuss power dissipation.…”

Computer-Aided 3D ICs Layout Design

“…The generation of a sophisticated 3D environment sometimes requires several years of work by a team of specialists, which is both very expensive and time consuming. That is why, the automatic generation of three-dimensional (3D) layout design solutions gains more and more attention, especially in the field of floorplanning of integrated circuits design [22] and architectural design [20].…”

“…Generally, floor plans are divided into two categories: the slicing and the non-slicing structure. A slicing floor plan is obtained by recursively bisecting a rectangle using a horizontal and/or vertical line [22]. The solution space is much smaller than in a non-slicing case which implies simpler data structures representation and faster runtime.…”