We present a placement-aware 3-D floorplanning algorithm that considers 3-D-placement of logic gates inside modules for wirelength minimization. It allows designers to introduce and evaluate an assignment of vertically-aligned parts of the same module to different device layers. A set of vertical constraints is derived on sequence pairs of different device layers that reduces the solution space, and a fast packing algorithm with vertical constraints enables quick floorplan evaluation. Experimental results on MCNC and GSRC benchmarks show that our algorithm can generate a good floorplanning solution with reduced wirelength inside modules and optimized footprint area while controlling the number of vias. Compared to the existing state-of-the-art 3-D floorplanning algorithms, our tool reduces the system level total wirelength by 9.8%.

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Through signal vias (TSVs) in 3D ICs suffer from thermo-mechanical stress, and may fail or attain plasticity resulting in significant yield loss. We present a novel set of strategies for yield improvement in the presence of defects in through signal vias in heterogeneous 3D system-on-chip. Monte-Carlo simulation results show that our strategy can improve the yield of 3D ICs significantly. Furthermore, we estimate the parametric yield and present a quantitative analysis of the impact of our approach on chip area, power, performance and chip revenue that can improve profitability. Our results suggest that the proposed strategies can be very useful in yield-aware 3D design.

The semiconductor industry has witnessed aggressive scaling of transistors following Moore's law, and has harnessed its benefits in terms of speed, density, and die size in the past several decades. At present transistor count has crossed one billion per chip, and transistor delay has been reduced to picoseconds range. However, the aggressive scaling has slowed down in deep submicron technology because of several challenges in VLSI design and manufacturability. Due to increasing power, performance, cost of fabrication, challenges in lithography, and other financial bottlenecks beyond 28nm, the industry has begun to look for alternative solutions. This has led to the current focus of the industry on Finally, we present a set of redundant via dependent analytical yield models for functional as well as parametric yield. The results obtained by the analytical models match closely with Monte Carlo simulation results. Thus they eliminate the need for computationally expensive Monte Carlo simulations. These analytical models can be used in fast estimation of yield, and can be used in yield-aware physical design such as 3-D floorplanning and P&R. We further derive an a~alytical model for a sweet spot between the numbers of fast/ slow chips obtained using our proposed solutions, and present an analytical model for the estimation of total chip revenue. The total chip revenue model takes the prices of fast and slow chips as input, and for a given TSV defect rate and our redundancy con~guration, it estimates the total number of fast/ slow chips in a bin for the total chip revenue estimation. DEDICATIONThis dissertation is dedicated to my parents. ACKNOWLEDGMENTS