Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet

Abstract

We describe a novel methodology to exploit the widely used Dynamic Partial Reconfiguration (DPR) support in Field Programmable Gate Arrays (FPGAs) to implant a hardware Trojan in an Advanced Encryption Standard (AES) encryption circuit implemented on a FPGA. The DPR is performed by transferring the required partial configuration bitstream file over an Ethernet connection to the FPGA board, from an attacker's computer which can communicate with the FPGA over a network. The inserted Trojan launches a "fault attack" on the AES encryption circuit, which enables recovery of the secret key by standard mathematical analysis of the faulty ciphertext produced. To the best of our knowledge, this is the first reported attack which exploits DPR to break an AES hardware implementation on FPGA. Our implementation results establish this to be an extremely potent attack on AES at low hardware and computational overhead, while using the standard unlicensed FPGA design tools.

The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA

“…In [19], the authors have designed a Trojan on a Basys FPGA board which gets triggered depending upon the "content and timing" of the signals. On the other hand, authors in [20] have designed a hardware Trojan which can be deployed on the FPGA via dynamic partial reconfiguration to induce faults in an AES circuitry for differential fault analysis.…”

Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications

“…The other important aspect of our target architecture is the management of the data (both DPR and cryptographic) that is transferred to the FPGA via the Ethernet API controller. A popular choice is the open-source Simple Interface for Reconfigurable Computing (SIRC) platform [13,9,10]. SIRC consists of both software and synthesizable hardware components and facilitates the seamless transfer of arbitrary data to an FPGA via high-level C++ API calls.…”

“…The HTH can be remotely triggered using DPR to maliciously alter the working of the cryptographic circuit on the fly, without the need for any dedicated conditional trigger circuit to be present on the FPGA. This reduces the attack overhead, makes the attack model more practical, efficient and challenging to debug and defend against [9,10]. In this paper, we focus on two such instances of remote Trojan insertion that remotely configure the output of the DCM to compromise the security of cryptographic modules:…”

“…cryptographic hashes) of possible hardware modifications to the system after successful passing of the design through HTH validations mechanisms. Any attempted DPR is allowed to modify the hardware if the signature of the partial bitstream matches with any of the pre-stored values [9].…”

“…This survey also says that "The IoT is and will be a great security challenge and an opportunity for new ways of thinking about ecologies of security". To the best of our knowledge, the idea of using remote DPR for inserting Hardware Trojan Horse (HTH) was first reported in [9]. This work implants an add-on HTH remotely via DPR by transferring bitstreams corresponding to a malicious HTH.…”