Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment

Amendola, A.M.; Benso, Alfredo; Corno, Fulvio; Impagliazzo, L.; Marmo, P.; Prinetto, P.; Rebaudengo, Maurizio; Reorda, M. Sonza

doi:10.1109/eurdac.1996.558255

Cited by 21 publications

(14 citation statements)

References 9 publications

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“…Considering the prevalence of hardware description languages throughout all phases of the IC design process, defect modeling with VHDL is a compelling idea that has been evolving steadily over the past several years [5][6][7][35][36][37][38][39][40][41][42][43][44][45]. VHDL is a popular and standardized hardware description language, used extensively in design specification, analysis, synthesis, and functional test generation.…”

Section: Defect-injectable Vhdl Cell Modelsmentioning

confidence: 99%

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

Shaw¹,

Al-Khalili

Rozon

2006

Integration

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Section: Defect-injectable Vhdl Cell Modelsmentioning

confidence: 99%

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

Shaw¹,

Al-Khalili

Rozon

2006

Integration

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“…Usually, these faults models assume a common type for the hardware faults (e.g. bit-flips or stuck-at faults) and inject them within the system following random distributions for the location and time of occurrence of the faults [7,8].…”

Section: Introductionmentioning

confidence: 99%

On The Development Of Fault Injection Profiles

Huang

Rodrı́guez

Li³

et al. 2007

2007 Proceedings - Annual Reliability and Maintainability Sympsoium

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The impact of hardware failures on software has attracted substantial attention in the study of dependable systems. Fault injection techniques have emerged as a major means to evaluate software behavior in the presence of hardware failures. However, due to the lack of knowledge of the fault distribution information, the fault location and time are randomly selected. One major drawback of this approach is that the injected faults do not represent the system's operational situation, thus software reliability cannot be credibly assessed. This paper aims at extending the use of fault injection to the reliability prediction of hardware faults. To do so, we have developed a set of analytical and simulation based methods capable of statistically reproducing the underlying physics and phenomena leading to hardware failures in a given system operational context. Such distributions are referred to as fault injection profiles, and are the basis to extend the fault injection technique with fault models that represent the actual conditions under which hardware faults occur.

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“…In the remaining techniques, the original VHDL code of the model is modified, either inserting saboteurs [6], [11], [12] or mutating the components of the model [6], [13], [14]. The techniques labeled as Other techniques are implemented by extending the VHDL language, either by adding new data types and signals, or modifying the VHDL resolution functions [7], [15].…”

Section: Introductionmentioning

confidence: 99%

Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code

Baraza

Gracia

Clavero

et al. 2008

IEEE Trans. VLSI Syst.

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1  Abstract-Deep submicron devices are expected to be increasingly sensitive to physical faults. For this reason, faulttolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior concern in the design process. Fault injection techniques based on the use of hardware description languages offer important advantages with regard to other techniques. Firstly, as this type of techniques can be applied during the design phase of the system, they permit reducing the time-to-market. Secondly, they present high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high fault modeling capability. However, implementing automatically these techniques in a fault injection tool is difficult. Especially complex are the insertion of saboteurs and the generation of mutants. In this paper we present new proposals to implement saboteurs and mutants for models in VHDL which are easy-to-automate, and whose philosophy can be generalized to other hardware description languages.Index Terms-Logic design, very large scale integration, physical faults, fault tolerance, dependability validation, hardware description languages, VHDL-based fault injection, saboteurs, mutants.

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Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment

Cited by 21 publications

References 9 publications

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

On The Development Of Fault Injection Profiles

Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code

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