Fault diagnosis for mixed-signal electronic systems

Chakrabarti, S.; Cherubal, S.; Chatterjee, Abhijit

doi:10.1109/aero.1999.789776

Cited by 20 publications

(17 citation statements)

References 12 publications

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“…For both the FDT and SDT, two different techniques are possible to apply: simulation before test (SBT) and simulation after test (SAT) (Chakrabarti et al, 1999). The first one concerns the type of simulation where calculations are conducted using the system's model, before the actual object is analyzed.…”

Section: Diagnostic Principlesmentioning

confidence: 99%

Automatic parametric fault detection in complex analog systems based on a method of minimum node selection

Bilski

Wojciechowski

2016

International Journal of Applied Mathematics and Computer Science

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The aim of this paper is to introduce a strategy to find a minimal set of test nodes for diagnostics of complex analog systems with single parametric faults using the support vector machine (SVM) classifier as a fault locator. The results of diagnostics of a video amplifier and a low-pass filter using tabu search along with genetic algorithms (GAs) as node selectors in conjunction with the SVM fault classifier are presented. General principles of the diagnostic procedure are first introduced, and then the proposed approach is discussed in detail. Diagnostic results confirm the usefulness of the method and its computational requirements. Conclusions on its wider applicability are provided as well.

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Section: Diagnostic Principlesmentioning

confidence: 99%

Automatic parametric fault detection in complex analog systems based on a method of minimum node selection

Bilski

Wojciechowski

2016

International Journal of Applied Mathematics and Computer Science

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“…There is a need of a GPF model for the purpose of the analysis of a GPF influence on the tested circuit [1,2,34]. This model has been created with a several assumptions based on the AIC fabrication process character.…”

Section: Terms and Definitionsmentioning

confidence: 99%

“…This model has been created with a several assumptions based on the AIC fabrication process character. The most important was presuming that all circuit parameters are manufactured in a single, multistage process [2,3,[28][29][30][31].…”

Section: Terms and Definitionsmentioning

confidence: 99%

“…-AIC are relatively small (single millimeters) thus the number of and the access to test pads is limited [1][2][3][4]. -The character of faults in AIC is different from discrete analogue circuits which results from the manufacturing process.…”

Section: Introductionmentioning

confidence: 99%

“…-The fault influence is propagated toward both input and output of the circuit. -Analogue signals are complex and continuous [1][2][3][4][5][6][7][8][9][10][11][12][13][14] in their nature.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuits

Jantos¹,

Grzechca²,

Rutkowski³

2012

Bulletin of the Polish Academy of Sciences: Technical Sciences

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Abstract. An evolutionary method for analogue integrated circuits diagnosis is presented in this paper. The method allows for global parametric faults localization at the prototype stage of life of an analogue integrated circuit. The presented method is based on the circuit under test response base and the advanced features classification. A classifier is built with the use of evolutionary algorithms, such as differential evolution and gene expression programming. As the proposed diagnosis method might be applied at the production phase there is a method for shortening the diagnosis time suggested. An evolutionary approach has been verified with the use of several exemplary circuits -an oscillator, a band-pass filter and two operational amplifiers. A comparison of the presented algorithm and two classical methods -the linear classifier and the nearest neighborhood method -proves that the heuristic approach allows for acquiring significantly better results.

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An unconditionally sound algorithm for testability analysis in linear time‐invariant electrical networks

Fontana

Luchetta

Manetti

et al. 2015

Circuit Theory & Apps

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Summary The issue of testability, intended as a measure of solvability of the parametric fault diagnosis problem in analog linear time‐invariant electrical networks, is addressed in this paper. Independently of the considered fault location method, such important metric provides information as to how many and which components can be diagnosed. For the reader's convenience and to set up an appropriate framework for our main achievements, our first concern is to rederive fundamental results concerning analog linear time‐invariant electrical network testability hinging on multifrequency measurements. Then a novel algorithm for testability analysis is proposed, which is straightforward and able to circumvent the main drawbacks of formerly proposed methods, such as computational and conceptual complexities, proneness to roundoff errors, and vulnerability to particular cases. A computer program that implements such algorithm is also described. Moreover, the possibility of employing further simplified versions of the latter and their links with a previously proposed approach are discussed on rigorous bases. Finally, examples are provided, which show the effectiveness and robustness of the new algorithms, also by means of a comparison with the old ones. Copyright © 2015 John Wiley & Sons, Ltd.

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Fault diagnosis for mixed-signal electronic systems

Cited by 20 publications

References 12 publications

Automatic parametric fault detection in complex analog systems based on a method of minimum node selection

Automatic parametric fault detection in complex analog systems based on a method of minimum node selection

Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuits

An unconditionally sound algorithm for testability analysis in linear time‐invariant electrical networks

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