Fault Injection and Test Approach for Behavioural Verilog Designs using the Proposed RASP-FIT Tool

Abstract

Soft-core processors and complex Field Programmable Gate Array (FPGA) designs are described as an algorithmic manner, i.e. behavioural abstraction level in Hardware Description Languages (HDL). Lower abstraction levels add complexity and delays in the design cycle as well as in the fault injection approach. Therefore, fault simulation/emulation techniques are demanded to develop an approach for testing of design and to evaluate dependability analysis of FPGA designs at this abstraction level. Broadly, the fault injection techniques for FPGA-based designs at the HDL code level are categorised into emulation and simulation-based techniques. This work is an extension of our previous methodologies developed for FPGA designs written at data-flow and gate abstraction levels under the proposed RASP-FIT tool. These methodologies include fault injection by code parsing of the SUT, test approach for finding the test vectors using dynamic and static compaction techniques, fault coverage, and compaction ratio directly at the code level of the design. In this paper, we described the proposed approaches briefly, and the enhancement of a Verilog code modifier for the behavioural designs is presented in detail.

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

“…The main advantage of fault injection at the code level is to create the state of the art methods and also develop the new methods with little effort. More details about this tool can be found in [11], [12], [13], [15], [16].…”

“…These modified designs are now used for the fault simulation/emulation, digital testing and dependability analysis, with FPGA tools, without much effort. The development of this tool is presented in previous research [11], [12], [15], [13], [16], [17], [18]. In this paper, serial fault simulation is validated for ISCAS'85 benchmark designs.…”

“…In previous research, Khatri et al proposed and developed a fault injection tool and named it RASP-FIT (RechnerArchitektur und SystemProgrammierung-Fault Injection Tool) tool [10], [11], [12], [13], [14], [15], [16]. This tool is used to instrument the Field Programmable Gate Array (FPGA) based designs.…”

A Technical Guide for the RASP-FIT Tool

“…These modified designs help design and test engineers to perform fault simulation, digital testing and dependability analysis without much effort. Verilog HDL code modification techniques for each abstraction level are presented in [21], [25], [26]. Along with the faulty copies, the RASP-FIT also provides the number of copies generated, the number of faults per copies which is used to calculate the number of select port pins, the number of total defects injected in the design.…”

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

“…Due to this, it decreases the time to market and increases design flexibility. The FPGA has been involved in various applications in the last couple of decades, such as communication, medical imaging, safety-critical applications [4], [5], [6], [7]. These applications are implemented on Static Random Access Memory (SRAM)-based FPGA.…”