Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells

Roscian, Cyril; Sarafianos, Alexandre; Dutertre, Jean-Max; Tria, Assia

doi:10.1109/fdtc.2013.17

Cited by 68 publications

(50 citation statements)

References 15 publications

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“…It allowed the authors of [9] and [10] to explain the counterbalancing effect that leads to the masking of the MP2 drain sensitive area and also to explain the infeasibility of bit-flip type faults. [10] reports similar experiments conducted on the RAM of a 0.35 µm CMOS technology commercial microcontroller using the same laser settings. The results are shown in figure 8 (the size of one SRAM cell is highlighted with a black square).…”

Section: A Simulation Resultsmentioning

confidence: 99%

“…During their experiments Roscian et al [10] used a 1064 nm laser source, a 1 µm spot size, and a pulse duration of 50 ns. Their target was a 5 transistors SRAM cell designed in CMOS 0.25 µm technology (see figure 4).…”

Section: Previous Work For 50 Ns Pulse Durationmentioning

confidence: 99%

“…Note that MP2's drain has a drain surface smaller than that of MN2/MN3 which makes this phenomenon happen (the photocurrent magnitude is proportional to the drain surface). Figure 6 from [10] reports the obtained lasersensitivity map of the SRAM cell at 0.42 W laser power. Fig.…”

Section: Previous Work For 50 Ns Pulse Durationmentioning

confidence: 99%

“…In previous works, Sarafianos et al [9] and Roscian et al [10] both studied the fault models that apply to SRAM cells for laser-induced faults. They drew maps of the lasersensitive areas of a 5 transistors SRAM cell using a 50 ns laser pulse duration.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses

Lacruche

Borrel

Champeix

et al. 2015

2015 IEEE 21st International on-Line Testing Symposium (IOLTS)

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Abstract-Laser fault injection into SRAM cells is a widely used technique to perform fault attacks. In previous works, Roscian and Sarafianos studied the relations between the layout of the cell, its different laser-sensitive areas and their associated fault model using 50 ns duration laser pulses. In this paper, we report similar experiments carried out using shorter laser pulses (30 ps duration instead of 50 ns). Laser-sensitive areas that did not appear at 50 ns were observed. Additionally, these experiments confirmed the validity of the bit-set/bit-reset fault model over the bit-flip one. We also propose an upgrade of the simulation model they used to take into account laser pulses in the picosecond range. Finally, we performed additional laser fault injection experiments on the RAM memory of a microcontroller to validate the previous results.

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Section: A Simulation Resultsmentioning

confidence: 99%

Section: Previous Work For 50 Ns Pulse Durationmentioning

confidence: 99%

Section: Previous Work For 50 Ns Pulse Durationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses

Lacruche

Borrel

Champeix

et al. 2015

2015 IEEE 21st International on-Line Testing Symposium (IOLTS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…The faults of input offset voltage in Fig .4(c) and (d) are in the same way. So for integrated operational amplifier circuit, the function fault model of output voltage limited to the power supply voltage and exorbitant offset voltage can be solved completely by drawing on the volt-ampere characteristics of the diode phase combined with the characteristics of the integrated circuit itself [12] . After a great deal of experiments and analysis, now there are 17 kinds of very-frequently used fault simulation model, including R_SHORT, R_OPEN, R_DRIFT Q_OPEN, Q_SHORT, D_OPEN, D_SHORT, GUGAO, GUDI, D_ERR, D_DELAY, D_CMOS_IN_ERR, D_CMOS_OUT_ERR, D_TTL_IN_ERR, D_OUT_ RES_DRIFT, D_IN_RES_DRIFT, D_TTL_OUT_ERR.…”

Section: ) Equivalent Circuit Methodsmentioning

confidence: 99%

Analog Circuit Fault Simulation Approach Based on Pspice Engine

Wang¹,

Zhao²,

Li³

et al. 2015

Proceedings of the 2015 International Conference on Mechatronics, Electronic, Industrial and Control Engineering

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Abstract-Pspice engine which possesses powerful modeling and simulation functions is widely used to analog circuit simulation, while can not be provided with fault simulation function. This paper addresses the problem of how to performance analog circuit fault simulation by calling Pspice engine. Firstly, the principle of the fault simulation was introduced. Under the supervision of the controller, the system carries out fault injection automatically into the target circuit, calls kernel spice3f5 simulation engine and realizes analog circuit fault simulation. Secondly, after analyzing the typical failure mode of components and the way to trigger fault, two methods of the substitution method and the equivalent circuit method are used to build the fault model libraries which conform to the simulator. At last, an experiment is designed to validate the validity and practicability of the proposed method, proving that the method can reduce the computational complexity and improve the simulation speed and the degree of fault isolation.

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Fault-Enabled Chosen-Ciphertext Attacks on Kyber

Hermelink¹,

Pessl²,

Pöppelmann³

2021

Lecture Notes in Computer Science

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NIST's PQC standardization process is in the third round, and a first final choice between one of three remaining lattice-based keyencapsulation mechanisms is expected by the end of 2021. This makes studying the implementation-security aspect of the candidates a pressing matter. However, while the development of side-channel attacks and corresponding countermeasures has seen continuous interest, fault attacks are still a vastly underdeveloped field. In fact, a first practical fault attack on lattice-based KEMs was demonstrated just very recently by Pessl and Prokop. However, while their attack can bypass some standard fault countermeasures, it may be defeated using shuffling, and their use of skipping faults makes it also highly implementation dependent. Thus, the vulnerability of implementations against fault attacks and the concrete need for countermeasures is still not well understood. In this work, we shine light on this problem and demonstrate new attack paths. Concretely, we show that the combination of fault injections with chosen-ciphertext attacks is a significant threat to implementations and can bypass several countermeasures. We state an attack on Kyber which combines ciphertext manipulation-flipping a single bit of an otherwise valid ciphertext-with a fault that "corrects" the ciphertext again during decapsulation. By then using the Fujisaki-Okamoto transform as an oracle, i.e., observing whether or not decapsulation fails, we derive inequalities involving secret data, from which we may recover the private key. Our attack is not defeated by many standard countermeasures such as shuffling in time or Boolean masking, and the fault may be introduced over a large execution-time interval at several places. In addition, we improve a known recovery technique to efficiently and practically recover the secret key from a smaller number of inequalities compared to the previous method.

show abstract

Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells

Cited by 68 publications

References 15 publications

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses

Analog Circuit Fault Simulation Approach Based on Pspice Engine

Fault-Enabled Chosen-Ciphertext Attacks on Kyber

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