Fault modeling and test algorithm development for static random access memories

Dekker, R.; Beenker, F. P. M.; Thijssen, L.

doi:10.1109/test.1988.207820

Cited by 150 publications

(34 citation statements)

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“…Testing them under worst case conditions (called 'burn-in') to accelerate failure is also not very reliable because it is known precisely how chips age under burn-in conditions with regard to static data losses. Dekker [7,8] described how to detect static data losses in SRAMs with 100 GO resistors as pull-up devices. Dekker noticed a broken pull-up resistor to cause a static data loss in about 100 ms.…”

Section: Testing For Static Data Lossmentioning

confidence: 99%

“…Variations in process parameters are seen to result in delay faults. Another peculiar fact observed in GaAs SRAMs is that data retention faults have an entirely new mechanism, apart from the stuck-open mechanism observed in silicon [7,14]. Parametric test procedures for these faults are described shortly.…”

Section: Faults In Gallium Arsenide (Gaas) Srams and Their Testingmentioning

confidence: 99%

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Technology and layout-related testing of static random-access memories

Chakraborty

Mazumder

1994

J Electron Test

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Abstract. Static random-access memories (SRAMs) exhibit faults that are electrical in nature. Functional and electrical testing are performed to diagnose faulty operation. These tests are usually designed from simple fault models that describe the chip interface behavior without a thorough analysis of the chip layout and technology. However, there are certain technology and layout-related defects that are internal to the chip and are mostly time-dependent in nature. The resulting failures may or may not seriously degrade the input/output interface behavior. They may show up as electrical faults (such as a slow access fault) and/or functional faults (such as a pattern sensitive fault). However, these faults cannot be described properly with the functional fault models because these models do not take timing into account. Also, electrical fault models that describe merely the input/output interface behavior are inadequate to characterize every possible defect in the basic SRAM cell. Examples of faults produced by these defects are: (a) static data loss, (b) abnormally high currents drawn from the power supply, etc. Generating tests for such faults often requires a thorough understanding and analysis of the circuit technology and layout. In this article, we shall examine ways to characterize and test such faults. We shall divide such faults into two categories depending on the types of SRAMs they effect-silicon SRAMs and GaAs SRAMs.

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Section: Testing For Static Data Lossmentioning

confidence: 99%

Section: Faults In Gallium Arsenide (Gaas) Srams and Their Testingmentioning

confidence: 99%

Technology and layout-related testing of static random-access memories

Chakraborty

Mazumder

1994

J Electron Test

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“…Several innovative test algorithms for random access memories have been reported [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. These algorithms can be categorized into two classes.…”

mentioning

confidence: 99%

“…One set of algorithms is based on the memory fault model as given by Nair, Thatte and Abraham [3]. The representative papers are [3][4][5][6][7][8][9][10][11]. A second class of test algorithms is based on the pattern sensitive neighborhood cell fault model of Hayes [12][13].…”

mentioning

confidence: 99%

STD Architecture: A Practical Approach to Test M-Bits Random Access Memories

Rajsuman

Rajkanan²

1994

VLSI Design

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“…In addition, tests for NPSFs do not detect many of the classical faults which also apply to SRAMs [3]; e.g., address decoder faults 'AFs', data retention faults 'DRFs' [9], stuck-open faults 'SOFs' [9], and coupling faults. Pseudo-random memory tests [10,11] do not require knowledge of the physical topology of the memory cell array and can be applied to memories with w-bit words (w 2); however, they have the disadvantage that their fault coverage is probabilistic.…”

Section: Introductionmentioning

confidence: 99%