Testing static random access memories (SRAM's) for all possible failures is not feasible. We have to restrict the class of faults to he considered. This restricted class is called a fault model. A fault model for SRAM's is presented based on physical spot defects, which are modeled as local disturbances in the layout of an SRAM. Two linear test algorithms are proposed, that cover 100% of the faults under the fault model. A general solution is given for testing word oriented SRAM's. The practical validity of the fault model and the two test algorithms are verified by a large number of actual wafer tests and device failure analyses.

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