Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

Suma, M S

doi:10.5121/vlsic.2011.2406

Cited by 2 publications

(1 citation statement)

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“…The outcome of achieved using the proposed methodology, fault covering was established with the help of the fault model generated using RTL that was compared with the fault detection in the gate level. However, this approach was not tested on the complex sequential circuits [9]. Another principal objective of RTL is to cut the time required for DFT that in turn reduces the time to market.…”

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confidence: 99%

Fault simulation for design for testability inserted designs

Gowda

Jamuna²

2023

IJEECS

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<p>Systematic design for testability (DFT) is a technique to enhance the testability of design so that it is further organized and self-regulating. The objective of systematic DFT is to enhance a circuit's operability and evidence. This can be performed in a variety of ways. The scan pattern method is the extremely predominant, and it modifies the design's internal sequential circuitry. In this manuscript, frequently used industry standard functional register-transfer level (RTL) designs are chosen. Structured DFT approach is adopted to do scan insertion and automatic test pattern generation (ATPG) to enhance the testability. Proposed methodology provides the controllability and observability for the clocks and reset used in chosen RTL designs by eliminating S rule and D rule violations by adding test logic. Also able to insert stuck at faults and achieve fault coverage of 97.78% and test coverage of 99.26% for DFT architecture for Wallace tree multiplier design, and found different classes of faults as testable and untestable faults and also performed fault simulation for the intended designs to detect fault from the created deterministic patterns.</p>

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confidence: 99%