Multiplication is an operation much needed in Digital Signal Processing for various applications. This paper puts forward a high speed Vedic multiplier which is efficient in terms of speed, making use of Urdhva Tiryagbhyam, a sutra from Vedic Math for multiplication and Kogge Stone algorithm for performing addition of partial products and also compares it with the characteristics of existing algorithms. The below two algorithms aids to parallel generation of partial products and faster carry generation respectively, leading to better performance. The code is written in Verilog HDL and implemented on Xilinx Spartan 3 and Spartan 6 FPGA kit using Xilinx ISE 9.1i. The propagation delay of the implemented architecture is obtained to be 28.699ns and 15.752ns respectively.

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As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to

16B/20B code is particularly well suited for highspeed local area networks and similar data links, where the information format consists of packets, variable in length, from about a dozen up to a several hundred 16-bit bytes. This transmission code translates each source byte into a constrained 20-bit binary sequence, which has excellent performance parameters near the theoretical limits for 16B/20B codes. The max run length is 5 and the maximum digital sum variation is 6. A very simple implementation of the code has been accomplished by partitioning the coder into 5B/6B and 3B/4B subordinate coders and by combining two 8B/20B modules side-by-side. This paper talks of 16B/20B CODEC development which is targeted to ASIC.