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Mammography, which is also calledMastography, is the process of using low-energy X-rays to inspect the human breast for screening and diagnostics. The purpose of mammography is to detect breast cancer early, usually by looking for specific lumps or microcalcifications. The X-rays used are usually around 30 kVp. Excessive voltage to such a machine would be harmful to the patient. Proper monitoring of temperature and pressure needs to be ensured. To ensure this, a start-up sequence module is developed. The start-up sequence module reads the digitized voltage, pressure, and temperature reading from the sensor and asserts all the outputs to ensure that the machine is ready. The scan chain is formed of 13 scan flip-flops in this configuration. The synthesis mapped the design to 484 instances of cells in the open-source PDK technology. The design had a total area of 594 μm2, with a cell width of 0.297 μm, and a height of 0.99 μm.

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Multipliers are the major contributors to the overall throughput in most SoCs. Vedic arithmetic is a novel and simplified approach to perform complex operations. Any good design must be targeted for optimal Speed-Area Trade-off. Commercial application demands reliable and economical design which makes testability an important parameter. Stuck-at-fault model for the design is to be developed and proper metrics have to be used to measure testability. Good design implies high fault coverage also. In this paper, design of Vedic multiplier with high fault coverage is proposed. Vedic multiplier designed using Urdhva-Triyagbhyam Sutra operates faster than the conventional multipliers like Booth and Array multipliers. Comparative analysis of VLSI parameters such as throughput, area and fault coverage is done with other multipliers.