Fault tolerant algorithms for network-on-chip interconnect

Pirretti, Matthew; Link, G.; Brooks, Richard; Narayanan, Vijaykrishnan; Kandemir, Mahmut; Irwin, M.J.

doi:10.1109/isvlsi.2004.1339507

Cited by 140 publications

(69 citation statements)

References 4 publications

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“…Works as in [17,18,29] leverage additional virtual channels to work around a few link failures. There has also been prior art that tackles the problem by flooding packets to random neighbors, hoping that they will eventually reach their destination [6,24]. Such approaches result in very low throughput during normal operation.…”

Section: Related Workmentioning

confidence: 99%

“…A number of resilient routing algorithms that can be applied to any irregular topology (i.e., a topology that survived after a number of random faults in network links) has been proposed in this domain, including up*/down* (introduced in Autonet) [27], segmentbased routing [23], FX routing [26], L-turn [21], and smartrouting [10]. During reconfiguration, the surviving topology is communicated to a central node, which runs the reconreliability performance area bounded faults early work [12,16], VCs [17,18,29] flooding [6,24] limited n/a n/a pattern constraints convex [9,31], L or T [9], polygons [20] limited n/a n/a unbounded faults off-chip routing [10,21,23 figuration algorithm in software. Using global knowledge of the functional links, the software computes new routing tables and communicates them back to each node.…”

Section: Related Workmentioning

confidence: 99%

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ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Aisopos

DeOrio

Peh

et al. 2011

2011 International Conference on Parallel Architectures and Compilation Techniques

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Abstract-Extreme transistor technology scaling is causing increasing concerns in device reliability: the expected lifetime of individual transistors in complex chips is quickly decreasing, and the problem is expected to worsen at future technology nodes. With complex designs increasingly relying on Networks-on-Chip (NoCs) for on-chip data transfers, a NoC must continue to operate even in the face of many transistor failures. Specifically, it must be able to reconfigure and reroute packets around faults to enable continued operation, i.e., generate new routing paths to replace the old ones upon a failure. In addition to these reliability requirements, NoCs must maintain low latency and high throughput at very low area budget.In this work, we propose a distributed reconfiguration solution named Ariadne, targeting large, aggressively scaled, unreliable NoCs. Ariadne utilizes up*/down* for fast routing at high bandwidth, and upon any number of concurrent network failures in any location, it reconfigures to discover new resilient paths to connect the surviving nodes. Experimental results show that Ariadne provides a 40%-140% latency improvement (when subject to 50 faults in a 64-node NoC) over other on-chip state-of-the-art fault tolerant solutions, while meeting the low area budget of on-chip routers with an overhead of just 1.97%.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Aisopos

DeOrio

Peh

et al. 2011

2011 International Conference on Parallel Architectures and Compilation Techniques

View full text Add to dashboard Cite

show abstract

“…Such stochastic-communication algorithm separates computation from communication and provides fault tolerance to on-chip failures [57,66]. However, to eliminate the high communication overhead of flood-based fault tolerance algorithm, Pirretti et al promoted a redundant random-walk algorithm which can significantly reduce the overhead while maintaining a useful level of fault tolerance [67]. However, the basic idea of sending redundant information via multipath to achieve fault tolerance may cause much higher traffic load in the network, and the probabilistic broadcast characteristic may also result in additional unpredictable behavior on network loading.…”

Section: Reliability Design In Nocmentioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2011

Journal of Electrical and Computer Engineering

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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“…The nodes communicate using a probabilistic broadcast: data packet is forwarded to a randomly chosen neighboring node until the entire network becomes aware of it. Directed flooding, probabilistic flooding and random walk are derived stochastic routing algorithms [14], [15]. The principal limitation of these algorithms is that they can only sustain a very low traffic injection rate.…”

Section: Related Work and Motivationmentioning

confidence: 99%

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

Shi

Zeng

2011

IEICE Trans. Inf. & Syst.

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SUMMARYManufacturing defects in the deep sub-micron VLSI process and aging resulted problems of devices during lifecycle are inevitable, and fault-tolerant routing algorithms are important to provide the required communication for NoCs in spite of failures. The proposed algorithm, referred to as scalable and reconfigurable fault-tolerant distributed routing (RFDR), partitions the system into nine regions using the concept of divideand-conquer. It is a distributed algorithm, and each router guarantees faulttolerance within one's own region and the system can be still sustained with multiple fault areas. The proposed RFDR has excellent scalability with hardware cost keeping constant independent of system size. Also it is completely reconfigurable when new nodes fail. Simulations under various synthetic traffic patterns show its better performance compared to Extended-XY routing algorithm. Moreover, there is almost no hardware overhead compared to Logic-Based Distributed Routing (LBDR), but the fault-tolerance capacity is enhanced in the proposed algorithm. Hardware cost is reduced 37 % compared to Reconfigurable Distributed Scalable Predictable Interconnect Network (R-DSPIN) which only supports single fault region.

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Fault tolerant algorithms for network-on-chip interconnect

Cited by 140 publications

References 4 publications

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Networks on Chips: Structure and Design Methodologies

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

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