Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

Abstract

Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, faulttolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant applicationspecific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a tablebased fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) -4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.

Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip

“…In this case, due to the limited scope of these values, the boundaries of the enumeration can be determined in advance. The range of possible values of the coefficients is given in Equation (3).…”

“…This allows the developer to abstract away from the physical implementation by performing design and modeling first at a high level, after which (if the network satisfies the design requirements) descending to a lower level of the HDL model. The approach where NoC design relies on a logical topology is called the Topological approach [3] and is described in Section 2.…”

“…For example, for a circulant with sixty-four nodes, the maximum number of neighborhoods 𝑑 will be six. For a two-dimensional circulant, the maximum number of neighborhoods can be estimated using Equation (3). In this case, it is equal to:…”