As the technology entering into Nano dimensions, the manufacturing processes are becoming less reliable, that is drastically impacting the yield. Therefore, fault tolerant systems are becoming more important, particularly in safety-critical applications. In this paper, we present the design and analysis of 4-bit Arithmetic and Logical Unit (ALU) circuit designed using CMOS 180 nm process technology for fault tolerant computing architectures. As, ALU is a functional block of the Central Processing Unit (CPU) of a computer system. It is highly recommended that the ALU block must be fault free or fault tolerant one. In order to have high reliability and high up time of the system, we have used the classical Triple Modular Redundancy (TMR) technique in which three redundant subsystems are used in order to attain high reliability. We have achieved lower power dissipation with higher reliability of ALU circuit. The Voter Logic and Fault detection circuits are also designed and reported in this paper.

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In this paper, an implementation of Dynamic Reconfigurable Touch Screen Keyboard (DRTSK) using a touch-screen panel and display are integrated in a development board is presented. An ARM920T based development kit (FriendlyARM) is programmed and implemented as a touch screen reconfigurable keyboard device. The FriendlyARM is interfaced with PC. The communication is through standard interfaces. The reconfigurable touch screen keyboard implemented on the hardware, tested under different operating systems and the functionality is validated.

In the recent year, many other new circuits are proposed using less number of transistors with less delay and very low power requirement. An adder with 10 transistors an adder with 8 transistors do not give full swing outputs for all input combinations and there is difference in output level for different combinations and these circuits have very low driving capabilities. Some other circuits are also proposed in but they do not give full swing output for all input combinations and power requirement is more. And these adders are not considered due to they do not provide full swing output. The Full Adder is designed using hybrid CMOS logic style by dividing it in three modules so that it can be optimized at various levels.[1] First module is an XOR-XNOR circuit, which generates full swing XOR and XNOR outputs simultaneously and have a good driving capability. It also consumes minimum power and provides better delay performance. Second module is sum circuit which is also a XOR circuit and uses carry input and the output of the first module as input to generate sum output. Third module is a carry circuit which uses the output of the first stage and other inputs to generate carry output. In the new full adder design new full adder circuit is proposed which reduce the power consumption, delay between carry out to carry in and PDP by 12 to 100%. Simulations are carried out on HSPICE using TSMC 0.12µm CMOS technology. So far designing the high performance arithmetic circuits minimization of the power and delay of the full adder circuit is required. This gives a new carry select full adder using this cmos full adder.

Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, faulttolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant applicationspecific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a tablebased fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) -4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.