Fault-tolerant architecture in a cache memory control LSI

Ooi, Y.; Kashimura, M.; Takeuchi, Hideki; Kawamura, Eiichi

doi:10.1109/4.126538

Cited by 15 publications

(5 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…For this scheme to work, cache line allocation (e.g., LRU or FIFO) has to be aware of the fault locations in a target set. Several circuit techniques have been studied for such LRU logic [Lamet and Frenzel 1993;Ooi et al 1992]. …”

Section: Line Deletementioning

confidence: 99%

Defcam

Lee

Cho

Childers

2011

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

Advances in deep submicron technology call for a careful review of existing cache designs and design practices in terms of yield, area, and performance. This article presents a Design and Evaluation Framework for defect-tolerant Cache Memories (DEFCAM), which enables processor architects to consider yield, area, and performance together in a unified framework. Since there is a complex, changing trade-off among these metrics depending on the technology, the cache organization, and the yield enhancement scheme employed, such a design flow is invaluable to processor architects when they assess a design and explore the design space quickly at an early stage. We develop a complete framework supporting the proposed DEFCAM design flow, from injecting defects into a wafer to evaluating program performance of individual processors on the wafer. Using DEFCAM, interesting interactions between architectural, organizational, and layout/defect related parameters can be easily evaluated. Moreover, we propose practical set remapping schemes to contain hard faults in cache memory. In a set remapping scheme, accesses that would go to an unusable faulty set are directed to a sound set. Case studies are presented to demonstrate the effectiveness of the proposed design flow and developed tools. Experimental results show that a set remapping is the most efficient fault covering method among prevailing strategies.

show abstract

Section: Line Deletementioning

confidence: 99%

Defcam

Lee

Cho

Childers

2011

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

show abstract

“…Therefore, the obvious solution to a faulty cache is to totally disable it. In set-associative caches, a less extreme solution is to disable one unit (way) of the cache [3].…”

Section: Previous Workmentioning

confidence: 99%

PADded cache: a new fault-tolerance technique for cache memories

Shirvani

McCluskey

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)

View full text Add to dashboard Cite

This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolerated or by the rapid degradation of performance as the number of faults increases. In this paper, we present a new technique that overcomes these two problems.This technique uses a special Programmable Address Decoder (PAD) to disable faulty blocks and to re-map their references to healthy blocks. Simulation results show that the performance degradation of direct-mapped caches with PAD is smaller than the previous techniques. However, for set-associative caches, the overhead of PAD is primarily advantageous if a relatively large number of faults is to be tolerated. The area overhead was estimated at about 10% of the overall cache area for a hypothetical design and is expected to be less for actual designs. The access time overhead is negligible.

show abstract

“…Thus, the yield of microprocessors with on-chip caches can be enhanced considerably if cache defects are tolerated without noticeable performance degradation. Many techniques have been proposed for disabling faulty cache blocks in partially good chips [3][4] [5] [9]. Since using a smaller cache memory does not affect the correct operation of a processor, the processor can still be used after some changes even if the cache contains manufacturing defects.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the most straightforward solution to fix a chip with a faulty cache is to disable the entire cache. For set-associative caches, a possible solution is to disable the cache-way which contains the defect [9]. A more sophisticated way is disabling only the defective cache-line because the existence of a defect in a cache-line does not affect other cache lines.…”

Section: Introductionmentioning

confidence: 99%

A cache-defect-aware code placement algorithm for improving the performance of processors

Ishihara¹,

Fallah²

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

View full text Add to dashboard Cite

Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that faultfree sections can function independently. Many fault tolerant techniques for improving the yield of processors with a cache memory have been proposed [3][4][5]. In this paper, we propose a defect-aware code placement technique which offsets the performance degradation of a processor with a defective cache memory. To the best of our knowledge, this is the first compiler-based technique which offsets the performance degradation due to cache defects. Experiments demonstrate that the technique can compensate the performance degradation even when 5% of cache lines are faulty. In some cases the technique was able to offset the impact even in presence of 25% faulty cache-lines.I.

show abstract

Fault-tolerant architecture in a cache memory control LSI

Cited by 15 publications

References 8 publications

Defcam

Defcam

PADded cache: a new fault-tolerance technique for cache memories

A cache-defect-aware code placement algorithm for improving the performance of processors

Contact Info

Product

Resources

About