Fault-tolerant array processors using single-track switches

Kung, Sun‐Yuan; Jean, S. N.; Chang, C. W.

doi:10.1109/12.21143

Cited by 135 publications

(41 citation statements)

References 16 publications

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“…The spare processors, the spare tracks, and the switches provide the necessary reconfiguration capability for the array and represent the hardware overhead for fault tolerance. Examples of special m-track designs are the 1-track design of [9], the 3-track design of [13], and our new 2-track design presented in Section 4.…”

Section: Motivation and Backgroundmentioning

confidence: 99%

“…We consider two types of models for incorporating fault tolerance into mesh systems, a``general m-track model,'' and a more specialized version of this model called a``special m-track model'' used in most previous work [9,13] and shown in Fig. 1; the FT designs based on these models are called general and special m-track designs, respectively.…”

Section: Motivation and Backgroundmentioning

confidence: 99%

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Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays

Mahapatra

Dutt

2001

Journal of Parallel and Distributed Computing

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Section: Motivation and Backgroundmentioning

confidence: 99%

Section: Motivation and Backgroundmentioning

confidence: 99%

Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays

Mahapatra

Dutt

2001

Journal of Parallel and Distributed Computing

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“…In redundancy approach, some PEs are dedicated as spare parts, and if these PEs cannot replace all the faulty ones, the chip has to be discarded. Various reconfiguration algorithms have been proposed in [26]- [29]. In the degradation approach, all PEs are treated in a uniform manner to derive a fault-free subarray, whose size is flexible.…”

Section: A Defect Tolerance In Memory and Vlsi Array Processorsmentioning

confidence: 99%

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Zhang

Han

et al. 2009

IEEE Trans. VLSI Syst.

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Abstract-Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. We propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture level. When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different. How to reconfigure the system with the most effective NoC topology is a relevant research problem. In this paper, we first show that this problem is an instance of a well known NP-complete problem. We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application software running on the processor. Experimental results show the effectiveness of the proposed techniques.

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“…Kung et al [4,5] proposed an architecture to realize an N x N array, where a row and a column of redundant PEs or two rows and columns of redundant PEs are added to an N x N array and the switching circuits are attached. In the architecture, 1 or 2 tracks and switching circuits are placed between PEs and the switching as well as shifting are executed according to the distribution of faults in order to achieve successful reconfiguration.…”

Section: Introductionmentioning

confidence: 99%

“…From such a viewpoint, many studies looked at how to reduce this complexity. In [4], the number of searches is reduced using the graph theory.…”

Section: Introductionmentioning

confidence: 99%

Wafer‐scale integration implementation of mesh‐connected multiprocessor systems

Numata

Horiguchi

1995

Systems & Computers in Japan

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SUMMARYWith recent advances in VLSI technology, WaferScale Integration implementation is becoming realistic, wherein massively parallel multiprocessors are implemented on a single wafer. As a result of this technique, the connections among VLSI become unnecessary and a high-speed, high-density system will be realized. This paper considers the mesh-connected network, which is one of the configurations of the massively parallel multiprocessor system, and discusses the reconfiguration techniques in realizing the network on the wafer. The reconfiguration technique is necessary for composing a system on a wafer, and several techniques have been proposed to date. Most of these, however, are based on global information or can be applied only to special cases. Consequently, they are not suitable for the self-reconfiguration scheme of a massively parallel system. From such a viewpoint, this paper proposes and evaluates an autonomic self-reconfiguration scheme using only local information, wherein the nondeterministic algorithm is added to the conventional method. It is seen as a result that the proposed method can realize a higher yield than the conventional method, as the array size becomes larger and the portion of the redundant PE becomes less. 1

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Fault-tolerant array processors using single-track switches

Cited by 135 publications

References 16 publications

Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays

Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Wafer‐scale integration implementation of mesh‐connected multiprocessor systems

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